Takaaki Nakazato

A process-variation-tolerant dual-power-supply SRAM with 0.179µm 2 Cell in 40nm CMOS using level-programmable wordline driver

A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel area saving. To improve the cell stability of the small channel area cell, we use a WL level-control scheme generated from dual power supplies in the WL driver. An adaptive WL-level programming scheme and dynamic-array-supply control increase SRAM operating margin. As a result, the cell failure rate is improved more than three orders of magnitude compared to the conventional dual-power-supply SRAM.

A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor

A 6-stage fully pipelined embedded SRAM is implemented in a 90nm SOI technology. The array uses a conventional 6-transistor memory cell and sense amplifier to achieve the cycle time while minimizing the impact of device variation. A sum-addressed pre-decoder allows partial activation for power savings.

Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor

The synergistic processor element is a new architecture oriented for multimedia and streaming processing. In this architecture, the memory is not a cache but a private or scratch pad memory. Such a memory is simple and needs to be high-frequency and large space in low-power. This design uses an 11 fan-out of four (11FO4), six-cycle, fully pipelined, embedded 256-Kbyte SRAM for this purpose. The designs memory is not one hard macro, but a group of custom macros physically distributed to optimize the pipeline.