Azuma Suzuki

A process-variation-tolerant dual-power-supply SRAM with 0.179µm 2 Cell in 40nm CMOS using level-programmable wordline driver

A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel area saving. To improve the cell stability of the small channel area cell, we use a WL level-control scheme generated from dual power supplies in the WL driver. An adaptive WL-level programming scheme and dynamic-array-supply control increase SRAM operating margin. As a result, the cell failure rate is improved more than three orders of magnitude compared to the conventional dual-power-supply SRAM.

World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS

Worlds first monolithically integrated Thin-Film-Transistor (TFT) SRAM configuration circuits over 90nm 9 layers of Cu interconnect CMOS is successfully fabricated at 300mm LSI mass production line for 3-dimensional Field Programmable Gate Arrays (3D-FPGA). This novel technology built over the 9th layer of Cu metal features aggressively scaled amorphous Si TFT having 180nm transistor gate length, 20nm gate oxide, fully silicided gate, S/D, all below 400C processing essential to not impact underlying Cu interconnects. Low temperature TFT devices show excellent NTFT/PTFT transistor Ion/Ioff ratios over 2000/100 respectively, operate at 3.3V, E-field scalable, and are stable for SRAM configuration circuits. We believe this 3D-TFT technology is a major breakthrough innovation to overcome the conventional CMOS device shrinking limitation.

A 0.7 V Single-Supply SRAM With 0.495

We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-supply operation.

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This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-k metal-gate CMOS technology with a 0.149µm2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.

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A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of SRAM sense amplifiers. The sense timing variation attributable to the random variation of transistor threshold voltage is reduced by sufficient count of multiple replica cells, and replica bitline delay is digitized and multiplied for adjusting it to the target sense timing. The variation of the generated timing was 34% smaller than that with a conventional technique and cycle time was reduced by 16% at the supply voltage of 0.6V in 40nm CMOS technology with this scheme.

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The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz. >

Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0.7 V single supply operation.

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm 2 cell in 32nm high- k metal-gate CMOS

An extended data retention (EDR) sleep mode with ECC and MT-CMOS is proposed for embedded DRAM power reduction. In sleep mode, the retention time improves by 8 times and the leakage current is reduced to 13% of the normal operation mode. Since ECC scrubbing operates only in the EDR sleep mode, read/write performance is not degraded. A 65nm low-power embedded DRAM macro featuring 400MHz operation and 0.39mW of data-retention power is realized

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

A description is given of a 4-Mb TTL (transistor-transistor logic) SRAM in 0.5- mu m BiCMOS technology which uses scaled-down features of optimized MOS and bipolar transistors and BinMOS circuits to achieve 9 ns access and low-power 3.3-V operation of a 16-b organization. The SRAM block diagram is presented, and the 0.5- mu m triple-polysilicon and double-metal BiCMOS process is summarized.<<ETX>>

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

A description is given of a 1-Mb*1ECL (emitter-coupled-logic) SRAM (static random access memory) fabricated with a 0.8- mu m BiCMOS technology which has 8-ns access time and is 10K-I/O (input/output) compatible. To achieve sub-10 ns address access time and low power consumption, an ECL CMOS level converter, a bit-line peripheral circuit, and an automatic power saving function are employed. Details of the 0.8- mu m BiCMOS process technology are summarized, and an oscilloscope photograph shows 8-ns address access time under nominal conditions. The RAM characteristics are summarized.<<ETX>>