Takahiro Hatano

A fingerprint verification algorithm using the differential matching rate

We propose a fingerprint verification algorithm with template matching based on the cyclic structure of the fingerprint image. For a correlation value between a template and a sensed image, we use the differential matching rate. The differential matching rate utilizes the cyclic structure observed in the local area of a fingerprint pattern, which is calculated by the maximum matching rate minus the minimum matching rate detected near the point where the matching rate is maximum. In order to extract the maximum effectiveness of the cyclic structure, we compare divided windows of a template image against a sensed image. A verification experiment confirmed that the proposed method judges whether a template image and a sensed image are same fingers fingerprints more accurately than the conventional method using the maximum matching rate as a correlation value. We obtain the equal error rate (EER) of 3.6%, which is better than half that of the conventional method.

Fingerprint image enhancement by pixel-parallel processing

This paper proposes a fingerprint image enhancement algorithm that can be mapped onto a compact pixel-parallel architecture, such as a fingerprint identification chip that senses and identifies fingerprints by itself. The algorithm is composed of two parts. First, ridges are enhanced by extracting their center lines and removing white noises using the center line image. Then valleys are enhanced by detecting areas where they are thin and disconnected and dilating them at these areas. Both enhancements are done with the structures of the fingerprint maintained. The experimental results show fingerprint identification using the proposed image enhancement algorithm improves the error ratio of that the conventional method, and the execution time is 0.14 msec when the proposed algorithm is performed on the array of processing elements on the fingerprint identification chip.

A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification

A 500-dpi cellular-logic processing array performs all fingerprint identification steps on one chip, from image acquisition, enhancement, to verification. Morphological functions for executing these steps are implemented in a 30/spl times/50-/spl mu/m/sup 2/ processing unit. A single-cycle datapath and a shared logic structure enable compact implementation of the processing unit. A fabricated 224/spl times/256-pixel fingerprint identification LSI demonstrates fully-functional image processing and practical accuracy of identification.

Sub 1-V 5-GHz-band up- and down-conversion mixer cores in 0.35-/spl mu/m CMOS

To lower the supply voltage and reduce the power dissipation of the RF front-end of wireless communication systems, a double-balanced square-law MOSFET mixer is proposed. It is applied to up- and down-conversion mixer cores. Implemented in a 0.35-/spl mu/m CMOS process, the up-conversion mixer core operates with a supply voltage of 0.5 V and a supply current of 0.8 mA in the 5-GHz band. The local leakage is suppressed below -40 dBc. The down-conversion mixer core drains 0.4 mA from a 1-V supply in the same band. The conversion gain is 6 dB and the 3rd-order input-referred intercept point (IIP3) is +5 dBm.

Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier

This paper presents fingerprint image enhancement and rotation schemes that improve the identification accuracy with the pixel-parallel processing of pixels. In the schemes, the range of the fingerprint sensor is adjusted to the finger state, the captured image is retouched to obtain the suitable image for identification, and the image is rotated to the correct angle on the pixel array. Sensor and pixel circuits that provide these operations were devised and a test chip was fabricated using 0.25-μm CMOS and the sensor process. It was confirmed in 150,000 identification tests that the schemes reduce the false rejection rate to 6.17% from 30.59%, when the false acceptance rate is 0.1%.

Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI

This paper describes logic and analog test schemes that improve the testability of a pixel-parallel fingerprint identification circuit. The pixel contains a processing circuit and a capacitive fingerprint sensor circuit. For the logic test, we propose a test method using a pseudo scan circuit to check the processing circuits of all pixels simultaneously. In the analog test, the sensor circuit employs dummy capacitance to mimic the state of a finger touching the chip. This enables an evaluation of the sensitivity of all sensor circuits on logical LSI tester without touching the chip with a finger. To check the effectiveness of the schemes, we applied them to a pixel array in a fingerprint identification LSI. The pseudo scan circuit achieved a 100% failure-detection rate for the processing circuit. The analog test determines that the sensitivities of the sensor circuit in all pixels are in the proper range. The results of the tests confirmed that the proposed schemes can completely detect defects in the circuits. Thus, the schemes will pave the way to logic and analog tests of chips integrating highly functional devices stacked on a LSI.

Hash-table and balanced-tree based FIB architecture for CCN routers

Recently, content centric networking (CCN) attracts attention as a next generation network on which every router forwards a packet to another router and also functions as a server. A CCN router has a forwarding table called FIB (Forwarding Information Base) but its table look-up can become a bottleneck. In this paper, we propose FIB data structure for CCN routers which can reduce the number of comparisons in its look-up table. Our proposed FIB is composed of a bloom filter and a hash table and each hash entry is connected to a balanced binary-search tree. By using our FIB, the number of comparisons cannot much increase even if hash collisions occur. Experimental results demonstrate the effectiveness of the proposed FIB over the several existing methods.