Takahiro Sakaguchi

A self-learning digital neural network using wafer-scale LSI

A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed. By using 0.8 mu m CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5 in silicon wafers. Neural functions and the back-propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30 cm cube. The dual-network architecture allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS). The high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI. This hardware can be connected to a host workstation and used to simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware. >

A self-learning neural network composed of 1152 digital neurons in wafer-scale LSIs

The design, fabrication, and evaluation of a compact self-learning neural network made up of more than 1000 neurons are described. A time-sharing bus architecture decreases the number of circuits required and makes possible flexible and expandable networks. Neural functions and the back propagation (BP) algorithm were mapped to binary digital circuits. A dual-network architecture allows high-speed learning. This hardware can be connected to a host workstation and used for a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware. The peak learning speed was about 10 times faster than BP simulation by an S-820 Hitachi supercomputer.<<ETX>>

Development of a high-performance general purpose neuro-computer composed of 512 digital neurons

A high-performance, general-purpose neuro-computer composed of 512 digital neurons is developed. Each neuron has an execution unit which is optimized for traditional neural functions, but the use of a micro-programming architecture makes it general enough to implement any neural function. Horizontal micro-instruction formats and massively parallel-pipelined computation allows high-speed on-chip learning. The theoretical maximum learning speed for the backpropagation algorithm is 1.25 GCUPS (giga connection updates per second). Eight digital neurons are integrated on each neuron chip by using 1.0-/spl mu/m CMOS technology, and 64 neuron chips are packaged in this hardware. This hardware can be connected to a host workstation by a SCSI network. We applied this neuro-computer to handwritten numerals recognition. The learning speed by using the neuro-computer is over 1000 times faster than by using the workstation.