Takahiro Yokoyama

High-efficiency low adjacent channel leakage GaAs power MMIC for 1.9 GHz digital cordless phones

We report on the fabrication of highly efficient GaAs MESFETs, the design for low distortion, and the performance of this MMIC. Two power MESFETs and input, interstage, and output matching circuits were integrated in a very small chip size of 1.0 mm/spl times/1.5 mm. This MMIC achieved an output power of 22 dBm at 1.9 GHz with high power added efficiency of 49.5% and low adjacent channel leakage power of -56 dBc under the low operating voltage of 3.0 V. This result represents one of the highest efficiencies that have been reported. This MMIC has a promising future for 1.9 GHz digital cordless phone applications. >

WSiN/SiO2 capped annealing for Si‐implanted GaAs

A new cap annealing method using WSiN/SiO2 multilayer film for Si‐implanted GaAs has been developed. The post‐implant annealing was performed by varying the SiO2 thickness in Ar/H2 atmosphere without As overpressure. The annealed layers were characterized by Hall effect, capacitance‐voltage, secondary ion mass spectrometry, and 77‐K photoluminescence measurements. The WSiN/SiO2 capped annealing method was found to offer high‐activation efficiency without the deep tailing of carrier concentration profiles. Enhanced activation efficiency with the increase in SiO2 thickness was also observed for this annealing method.

A low distortion GaAs quadrature modulator IC

A low distortion GaAs quadrature modulator IC with on-chip active 90/spl deg/ phase-shifter was fabricated by using high linearity GaAs MESFET technology for wideband wireless applications. The IC showed OIP3 of +16 dBm, CLR of -40 dBc, and IRR of -40 dBc at supply voltage of 5.0 V, dissipation current of 70 mA and carrier frequency of 600 MHz. Excellent EVM smaller than 1.0% and ACPR of 60 dBc were also obtained for 4 Mbps QPSK signal with Pout of -10 dBm.

Self-aligned emitter power HBT and self-aligned gate power HFET for low/unity supply voltage operation in PHS handsets

Abstract A new power HBT and HFET were developed for low unity supply voltage operation in PHS handsets. The emitter region, the emitter electrode, the buried collector and the base electrodes in the power HBT are formed using the emitter electrode self-alignment process in order to reduce parasitic resistance and capacitance. The wirings on each electrode of the HBT are formed by Au plating technique for high current operation. The gate electrode in the power HFET is self-aligned to the drain/source electrodes by using the drain/source contact mesas as a mask, where the distance between the drain and the source is minimized and the parasitic resistances are reduced. In addition, an asymmetrical double-doped structure of AlGaAs/GaAs/InGaAs/AlGaAs is applied to the HFET in order to obtain a high current density. Both the power HBT and HFET exhibited the knee voltage less than 1 V with the maximum current more than 500 mA. The power HBT performed a power gain of 14.2 dB, an efficiency of 33.8% and the power HFET performed 12.5 dB and 34.5%, with a sufficient margin of distortion for PHS standard at an output power of 22 dBm, a supply voltage of 3.5 V and a frequency of 1.9 GHz under the unity operation.

High-Current and High-Transconductance Self-Aligned P^+-GaAs Junction HFET of Complete Enhancement-Mode Operation

High-current and high-transconductance self-aligned p+-GaAs junction HFETs (PJ-HFETs) of a complete enhancement-mode operation have been developed for the first time. Due to the advantages of the p/n junction, the barrier height of 1.12 eV has been obtained. To obtain high activation for the Si implanted epitaxial layers, we optimized the annealing conditions. The 0.8 µm-gate complete enhancement mode PJ-HFET with a large forward gate voltage swing of more than 1.5 V exhibited a K-value of 400 mS/Vmm, a maximum transconductance (gmMAX) of 410 mS/mm and a maximum drain current (IMAX) of 380 mA/mm with a threshold voltage (Vth) of 0.2 V. The standard deviation of Vth was 18.4 mV across a 3 inch wafer. Operated with a drain bias of 3.3 V, the PJ-HFET demonstrated a power-added efficiency (PAE) of 39.5% with an adjacent channel leakage ratio (ACPR) of -57.4 dBc at an output power (Pout) of 21.5 dBm and a frequency of 1.9 GHz.