Tadashi Nishimura

Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFETs down to 0.1 mu m gate length

The subthreshold slope in ultra-thin-film fully depleted SOI MOSFETs is investigated for channel lengths from the long channel region down to 0.1 mu m. A doping effect is found which allows improvement of the S-factor by increasing the channel doping concentration. In order to explain this phenomenon and to clarify the mechanism of S-factor degradation at short gate lengths, a two-dimensional analytical model is developed. A modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide. It is found that the S-factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the two-dimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the subthreshold region. The analytical model results are compared to those of numerical device simulation, and a good agreement is found. >

Self-aligned silicide technology for ultra-thin SIMOX MOSFETs

The salicide technology using rapid thermal annealing was applied to MOSFETs on thin-film SOI. Since the SOI film was limited to a thickness of less than 100 nm, the silicidation reaction between Ti and Si atoms on the SOI surface exhibited new features that depended on the initial thickness of the deposited Ti. There was an optimum thickness of as-deposited Ti on silicidation due to the restricted thickness of the Si layer. Beyond the optimum point, the region adjacent to the silicided Si layer works as a Si source to assure stoichiometric TiSi/sub 2/. The subthreshold slopes and carrier mobilities were not changed by the salicide process. Junction leakage characteristics were slightly degraded; however, the change was small enough for device application. The influence on AC characteristics was well demonstrated for a high-speed CMOS ring oscillator with a gate length of 0.7 mu m. The minimum delay time/stage was 46 ps/stage at 5 V. This gives 1.8 times higher speed operation than the controlled bulk CMOS ring oscillators with the same design rule. >

Impact of a vertical /spl Phi/-shape transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond

We propose a Vertical /spl Phi/-shape Transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond. The V/spl Phi/T is a vertical MOSFET whose gate surrounds its channel region like a Greek alphabet /spl Phi/. It is built by penetration of the gate electrode (=word line) which has been formed beforehand. Application of the V/spl Phi/T for DRAM cell brings about cell size reduction to 50% and process simplification of about 10% at least. This is mainly because its bit line contact and the V/spl Phi/T are vertically aligned and storage node contact is eliminated. We have indicated that the V/spl Phi/T is an interesting candidate for the gigabit DRAM in view of size, cost and performance.<<ETX>>

A 209 k-transistor ECL gate array with RAM

The authors describe a gate array with an ECL (emitter-coupled-logic) cell structure for implementing a high-density configurable RAM. A unit based on a variable size cell is modified to achieve such a RAM. Every unit has an extra transistor buried under the power bus to eliminate area penalty. One memory bit is constructed using one buried transistor plus three transistors in a unit. An n-p-n transistor and a tap resistor load cell are employed for structural matching with the logic gates. Since the read current is supplied directly from the V/sub CC/ bus instead of the word line, the transistor size of the word-line driver is minimized. The standby and read currents are 120 mu A and 800 mu A, respectively. The decoder, sense amplifiers, and word-line drivers are implemented by logic gates. RAM size can be varied by each unit row; the bit increment is 144. The process employs double-polysilicon self-aligned technology with a silicide-base electrode of TiSi/sub 2/ and triple-layer metallization. The features of the gate array are listed.<<ETX>>

Novel SOI wafer engineering using low stress and high mobility CMOSFET with -channel for embedded RF/analog applications

For high performance RF/analog and logic device technology, novel SOI wafer engineering featuring <100>-channel SOI CMOSFET with high-resistivity substrate is proposed. Mobility of PMOSFET is improved about 16% by changing a channel direction from <110> to <100>. Moreover, the reduction of the drive current in narrow channel PMOSFET is suppressed. The maximum oscillation frequency (f/sub max/) for NMOSFET is improved around 7% by changing the buried oxide (BOX) thickness from 400 nm to 150 nm because the self-heating effect is suppressed, and is improved around 5% by changing the substrate resistivity from 10 /spl Omega/cm to 1000 /spl Omega/cm because the power loss is reduced. In this work, the wafer engineering which consists of 1) <100>-channel, 2) optimization of BOX, and 3) high resistivity substrate, is proposed to improve the RF performance of the CMOSFET.

16 Mb DRAM/SOI technologies for sub-1 V operation

Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFETs, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16 MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1 V.

ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation

An SOI-DRAM test device was fabricated on thin-film SOI (Silicon On Insulator) structure with 0.5 /spl mu/m CMOS/SIMOX (Separation by IMplanted OXygen) technology. Field-shield isolation and polysilicon pad techniques were introduced for the specific problems to thin-film SOI devices such as the floating body effects and increase of parasitic source/drain resistance, respectively. Keeping the thin-film SOI from etching off during DRAM cell processing was especially cared by using high-selectivity ECR etching technology. The bit-line capacitance of the experimental SOI-DRAM is reduced by 25% and the /RAS access time is 30% faster compared with the equivalent Bulk-Si DRAM. Low voltage DRAM operation down to 2 V range is also observed.<<ETX>>

CAD-compatible high-speed CMOS/SIMOX gate array using field-shield isolation

A specific 0.5 /spl mu/m CMOS/SIMOX technology was developed for a gate array/sea of gate (SOG) using field-shield (FS) isolation to overcome a pending problem of source-to-drain breakdown voltage (BV/sub ds/) lowering. FS isolation is capable of improving BV/sub ds/ because surplus holes generated by impact ionization at the drain region are collected through the body region under the FS gate. BV/sub ds/ was maintained at a level of junction breakdown before reaching the punchthrough limitation at a gate length of around 0.3 /spl mu/m using the FS isolation. The FS isolation technique was successfully applied to an SOG gate array on a SIMOX substrate. The gate array has the same area as that on the bulk-Si and is compatible to a conventional bulk-Si CAD system because the layout is basically the same. A 53-stage ring oscillator fabricated on the FS isolated SOG gate array exhibited 1.7 times higher speed operation than that on a bulk-Si counterpart, keeping low power consumption characteristics up to a drain voltage of 3 V. >

A 21-mW 4-Mb CMOS SRAM for battery operation

The authors describe a 21-mW 4-mB CMOS SRAM for the application of memory systems which operate on 3-V batteries. A low active power is achieved by novel circuit technologies. A thin-film transistor (TFT) load memory cell effectively reduces standby current to 0.4 mu A. A new multibit test circuit, which permits measurement of access time, is also introduced for a reduction of the test time. The authors describe the characteristics of the TFT memory cell and the improved memory cell design for stable cell operation. The 0.6- mu m process technology used to fabricate the 4-Mb SRAM and the chip performance are outlined. >

A bipolar 18K-gate variable size cell masterslice

An emitter-coupled logic (ECL) 100K compatible 18K-gate masterslice has been developed. A variable-size-cell (VSC) approach is proposed to reduce nonutilized elements in the ECL gate array. The concept of the VSC is to implement logic circuitry not by the usual macrocells but by newly developed cellular units. The unit is constructed using three transistors and four polysilicon resistors. By utilizing 1.2-/spl mu/m salicide base contact technology, the intrinsic gate delay is 150 ps at a power consumption of 2.4 mW. A 32-bit multiplier has been implemented as an application. Compared with conventional cell structures, a 20% higher effective gate density is achieved.