Takamaro Kikkawa

A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs

A novel capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) poly-Si storage node has been developed. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufacturable by optical delineation. The feasibility of the COB cell for 64-Mb DRAMs has been verified by a 64-kb test memory with 1.8- mu m/sup 2/ cells using a 0.4- mu m design rule, storage capacitance of 30 fF, 7-nm-SiO/sub 2/-equivalent dielectric film, and a storage node height of 0.5 mu m.<<ETX>>

Device application and structure observation for hemispherical‐grained Si

A polycrystalline‐silicon surface with hemispherical grains (HSG) is deposited by low‐pressure chemical vapor deposition at 590 °C. At the temperature, 590 °C, the structure of the Si film just after deposition is amorphous, but crystallization of the amorphous Si occurs to produce HSG‐Si during annealing after deposition. The HSG‐Si is formed by the nuclei generation on the clean amorphous‐Si surface and by the crystalline growth during annealing. The surface area of the HSG‐Si film is about twice as large as Si films deposited at other temperatures. By applying the HSG‐Si film as the storage electrode for a 64‐M‐bit dynamic random access memories (DRAM) stacked‐capacitor with a SiO2/Si3N4 dielectric film, a capacitance of twice the value is obtained. The increase of the capacitance makes it possible to reduce the DRAM cell area, even by using a relatively thick dielectric film for higher reliability.

High transmission gain integrated antenna on extremely high resistivity Si for ULSI wireless interconnect

We have demonstrated the highest transmission gain integrated dipole antenna on Si reported so far, to use as an integrated antenna for the purpose of ULSI on-chip wireless interconnection. A 2-mm long and 10-/spl mu/m wide dipole antenna pair at a distance of 1 cm shows a transmission gain of -36.5 dB at 18 GHz, which is 20 dB higher than the previously reported gain. This large increase in gain is achieved by proton implantation on the Si substrate, which increased the resistivity from 10 /spl Omega/-cm to 0.1 M/spl Omega/-cm. It is also found that transmission gain can be maximized for a given resistivity by optimizing the Si substrate thickness or by inserting a low-k dielectric layer below the substrate.

Gaussian Monocycle Pulse Transmitter Using 0.18

A single-chip Gaussian monocycle pulse (GMP) transmitter using 0.18 mum CMOS technology with an on-chip integrated antenna was developed for inter-chip ultra-wideband (UWB) communication. Ultra-short GMP signals of 280 ps duration, -20.2 dB ringing level and 3.6 GHz center frequency were generated with the power consumption of 12.6 mW at 1.8 V. Intra- and inter-chip transmissions and receptions of the generated GMP were successfully demonstrated at a pulse repetition rate of 1.16 Gb/s by use of on-ship integrated dipole antennas.

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A single-chip ultra-wideband (UWB) receiver was developed using 0.18 mum CMOS technology, and inter-chip wireless data communication by integrated antennas was confirmed. Timing pulse and data pulse with on-off keying were alternately sent from a transmitting antenna. Double Gaussian monocycle pulse (GMP) template generators performed detections of timing and data pulses. A single GMP template, whose probability distribution of the pulse repetition cycle is given by Gaussian, showed a random jitter of 4.87 ps. Dual-Dirac model could explain the probability distribution of the cycle of double GMP template. Obtained random jitter and deterministic jitter were 4.6 ps and 14.4 ps, respectively. The receiver successfully recovered 200 Mbps data at the distance of 0.5 mm.

CMOS Technology With On-Chip Integrated Antennas for Inter-Chip UWB Communication

A compact 4 × 4 planar ultrawideband (UWB) antenna array with the total size of 44 × 52.4 mm was developed for radar-based breast cancer detection system. The center frequency and the bandwidth of the antenna were 6 and 12.5 GHz, respectively. The breast phantom materials were developed to fit the characteristics of the measured human breast tissues. A quasi-three-dimensional confocal imaging was performed using the breast phantoms. It was confirmed that the compact 4 × 4 antenna array could detect a 5 × 5 × 5-mm3 tumor phantom in an inhomogeneous structure with a glandular phantom and resolve the two separate tumor phantoms, which were located at the depth of 23 mm with the spacing of 10 mm.

A Single-Chip Ultra-Wideband Receiver With Silicon Integrated Antennas for Inter-Chip Wireless Interconnection

The variability in measurements of complex permittivities of tumor tissues between multiple samples could be attributed to the volume fraction of cancer cells in the excised tumor tissue. By the use of a digital photomicrograph image and hematoxylin-eosin staining, it was found that the malignant tumor tissue was not fully occupied by the cancer cells, but the cells were distributed locally in the stroma cells depending on the growth of cancer. The results showed that the volume fraction of cancer cells in the tumor tissue had a correlation to the measured conductivity and dielectric constant in the frequency range from 1 GHz to 6 GHz. It introduces a method to understand and gauge variability in measurements between different tumors.

A Compact 4

An interconnection structure using a TiN/Al-1% Si-0.5% Cu/TiN/Al-1% Si-0.5% Cu/TiN/Ti multilayer conductor was investigated as a quarter-micrometer interconnection candidate for 256-Mb DRAMs. It was found that intermetallic compounds such as TiAl/sub x/ were formed at both grain boundaries of Al-Si-Cu and interfaces between Al-Si-Cu and TiN of the multilayer, resulting in both increase in Vickers hardness and suppression of stress relaxation. The multilayer conductor strip, which was covered with plasma-enhanced chemical vapor deposition silicon nitride (P-SiN), suppressed stress-induced voiding after heat treatment at 500 degrees C. Electromigration tests for quarter-micrometer wide multilayer strips indicated the improvement in the mean time to failure and the increase of the standard deviation. >

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Many-core chip design has become a popular means to sustain the exponential growth of chip-level computing performance. The main advantage lies in the exploitation of parallelism, distributively and massively. Consequently, the on-chip communication fabric becomes the performance determinant. In the meantime, the introduction of Ultra-Wideband (UWB) interconnect brings in the new opportunity for giga-bps communication bandwidth, milliwatts communication power, and low cost implementation for millimeter range on-chip communication for future chip generations. In this paper, we study multi-channel wireless Network-on-Chip (McWiNoC) with ultra-short RF/wireless links for multi-hop communication. We first present the benefit of high bandwidth, low latency and flexible topology configurations provided by this new on-chip inter-connection network. We then propose a distributed and deadlock-free location based routing scheme. We further design an efficient channel arbitration scheme to grant multi-channel access. With a few representative synthetic traffic patterns and SPLASH-II benchmarks, we demonstrate that McWiNoC can achieve 23.3% average performance improvement and 65.3% average end-to-end latency reduction over a baseline NoC of 8 × 8 metal wired mesh.

4 Planar UWB Antenna Array for 3-D Breast Cancer Detection

In this new fabrication technology for high-density DRAMs, an electrode with even-surface amorphous-silicon is changed to one with uneven-surface hemispherical-grained Si (HSG-Si). This fabrication method consists of easily controllable processes: formation of smooth amorphous Si electrodes by low-pressure chemical vapor deposition followed by removal of native oxide and high-vacuum annealing. This annealing process can form HSG-Si covering the entire surface of all types of storage electrodes, including side-wall surfaces which had previously been dry-etched. The resulting storage electrode with HSG-Si can store 1.8 times as much charge as can be stored on an electrode without HSG-Si. Such an increase makes it possible to reduce the height of storage electrodes. This technique is applicable to the fabrication of high-density DRAMs. >