Nobuo Sasaki

High performance poly-Si TFTs on a glass by a stable scanning CW laser lateral crystallization

We have developed high performance poly-Si TFTs, which have comparable performance to that of [100] Si-MOSFETs, by using a stable scanning DPSS CW laser lateral crystallization without introduction of thermal damage to 300/spl times/300 mm/sup 2/ glass substrates with process temperature below 450/spl deg/C.

Charge pumping in SOS—MOS transistors

The variation of the floating-substrate potential of SOS-MOS transistors is studied by applying frequent pulses to the gate. The minority carriers are injected into the floating substrate by charge pumping and they recombine there. The injected charges are stored because of the reverse-biased junctions at the source and drain. The threshold-voltage change by the substrate bias is also investigated. If the silicon film is fully depleted under the gate, the threshold-voltage change does not occur. This condition is used to stabilize the high-speed operations of the SOS-MOS integrated circuits. A new memory cell consisting of only one transistor without a storage capacitor is realized utilizing the change of the floating-substrate potential by the charge pumping and the avalanche multiplication. The sensitivity of the memory cell is affected by the channel length of an SOS-MOS transistor. The memory storage time is obtained as 300 µs.

Charge pumping SOS-MOS transistor memory

A new memory cell is proposed, utilizing the inherent features of the floating substrate of SOS-MOS transistors. The operations of the fabricated cell are also demonstrated. The potential of the floating substrate is found to be changed by the charge pumping action (WRITE 1). The injected charge is stored in the substrate due to the reverse-biased junctions at the source and drain (STORE), and is removed by the avalanche multiplication current (WRITE 0). The conditions to change the threshold voltage by the substrate bias is studied (READ). For the lower impurity concentration in the substrate or the higher substrate bias Vsub, it is found that threshold voltage is independent of Vsub.

Selective single-crystalline-silicon growth at the pre-defined active regions of TFTs on a glass by a scanning CW laser irradiation

We have developed a new Si crystallization method, which makes possible to form single-crystalline-silicon (Si) film in channel region of TFTs on non-alkali glass without introducing thermal damage into it, using a scanning solid-state CW laser (10 W). The peculiar characteristics of this crystallization method are introduction of pre-defined thick capping Si layer on the pre-patterned channel region and laser irradiation from back surface. We succeeded in formation of single-crystalline-Si with 1.5 /spl mu/m wide and 20 /spl mu/m long. High performance TFTs with mobility of 300 cm/sup 2//Vs, S-value 0.41 V/dec, Vth -0.5 V, and low off-current, were obtained by fabrication process below 450/spl deg/C. This crystallization uses stable solid-state laser and realizes the high-performance Si devices on non-alkali glass substrates, which are necessary to achieve System On Glass (SOG).

Mobility enhancement limit of excimer-laser-crystallized polycrystalline silicon thin film transistors

The effects of various carrier scattering mechanisms on excimer-laser-crystallized polycrystalline silicon (poly-Si) thin film transistors (TFTs) fabricated using 450u200a°C processes on a glass substrate were studied. Good performance of a separated by ion implanted oxygen (SIMOX) metal–oxide–semiconductor field-effect transistor (MOSFET) with field-effect mobility of 670 cm2/Vu200as and a subthreshold swing value of 0.087 V/dec was obtained using these 450u200a°C processes. The results showed the formation of a good silicon/silicon dioxide (SiO2) interface that is comparable to that of thermal oxide, as well as the high capability of 450u200a°C processes. The performance of the above SIMOX-MOSFET is superior to that of excimer-laser-crystallized poly-Si TFTs fabricated using the same 450u200a°C processes. This shows that poorer performance of poly-Si TFTs is caused by the poor crystalline quality of the poly-Si film. The field-effect mobility is affected little by the in-grain microdefects and surface morphology of the exc...

Higher harmonic generation in CMOS/SOS ring oscillators

Harmonic generation is found with 101-stage ring oscillators. Harmonics have not been observed for the usual ring oscillators with a small number of stages. If one mistakes the higher harmonic generation for the fundamental, he obtains a wrong propagation delay which is shorter than the real one. It is shown experimentally and theoretically that only odd harmonics are generated for the ring oscillators with an odd number of stages. The propagation delay t pd of the nth harmonic oscillation is given by t_{pd} = n cdot T/2N where T is the observed repetition period and N the number of stages. Computer simulation shows that a ring oscillator with an even number of stages can also oscillate if every inverter is the same, and that the oscillation decays if there is asymmetry in the inverter chain. If N is large and the effects of the deviations of the transistor parameters cancel one another, the harmonic oscillation that happens to be generated can continue.

Gettering of iron impurities in p/p+ epitaxial silicon wafers with heavily boron‐doped substrates

We studied gettering effects in p/p+ silicon epitaxial wafers that have no dislocations near the epi/sub interface and oxygen precipitates inside the p+ substrate. The wafers were contaminated with high‐ and low‐level Fe surface concentrations to clarify the relationship between gettering effects and Fe concentration. After annealing at 1000u2009°C for 60 min followed by quenching, the p/p+ epitaxial wafers showed the same gettering effect independent of the Fe contamination level. The intrinsic gettered reference wafers, however, did not show the gettering effect because Fe impurities do not supersaturate at 1000u2009°C. We concluded that the gettering effect of Fe in the p/p+ epitaxial wafers is due to the difference in solubility between the p epitaxial layer and the p+ substrate.

Laser recrystallization of Si over SiO2 with a heat‐sink structure

Complete single crystalline silicon films over SiO2 have been produced with a heat‐sink structure designed for best utilization of temperature gradients during resolidification process induced by an incident cw Ar laser beam. The structure includes device regions with thin SiO2 layers which act as a heat sink to the substrate and the peripheral regions with thick SiO2 layers. By using this technique, residual grain boundaries in the laser recrystallized silicon over insulator can be eliminated. N‐channel metal‐oxide‐semiconductor field‐effect transistors fabricated in the recrystallized silicon films with a heat‐sink structure exhibit good device characteristics, having a surface electron mobility of 500 cm2/Vu2009s which is comparable to that of bulk devices.

Low-power and high-stability SRAM technology using a laser-recrystallized p-channel SOI MOSFET

Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked over bottom n-channel bulk MOSFETs for both drivers and transfer gates. A sufficient laser power assures the same leakage currents between SOI MOSFETs fabricated on an undulated insulating layer in memory cell regions and on an even insulating layer in field regions. The on/off ratio of the SOI MOSFETs is increased by a factor of 10/sup 4/, and the source-drain leakage current is decreased by a factor of 10-10/sup 2/ compared with those of polysilicon thin-film transistors (TFTs) fabricated by using low-temperature regrowth of amorphous silicon. A test 256-kb SRAM fabricated this technology shows improved stand-by power dissipation and cell stability. The process steps can be decreased to 83% of those TFT load SRAMs if both the peripheral circuit and memory cells are made with p-channel SOI and n-channel bulk MOSFETs. >

Effect of silicon film thickness on threshold voltage of SOS-MOSFETs

Abstract The variation in threshold voltage tV th of silicon-on-sapphire MOSFETs (SOS-MOSFETs) is experimentally and theoretically studied as a function of the epitaxial film thickness t in the thickness range of 0.18–0.80 μm. Threshold voltages of both n - and p -channel MOSFETs are found to shift drastically toward the more enhancement mode as t decreases. This phenomenon is not explained by a variation of the doping concentration in the film nor by a change in the Siue5f8SiO 2 interface charge. A model of two deep levels (upper acceptorlike and lower donorlike) due to defects distributed exponentially in the film is presented, from whcih the V th are numerically obtained as a function of t . This treatment explains well the experimental shifts of V th