Takao Kihara

A multiband LTE SAW-less CMOS transmitter with source-follower-drived passive mixers, envelope-tracked RF-PGAs, and Marchand baluns

We present a multiband LTE SAW-less CMOS transmitter. Source followers, which drive passive mixers, contribute to the small-area and low-power transmitter. An envelope-tracking technique improves the linearity of RF programmable gain amplifiers, and Marchand baluns are suitable for multiband operation. The transmitter, which includes digital-to-analog converts and a phase-locked loop, covers 700 MHz to 2.6 GHz with −42 dBc ACLR. RX-band noise of −161 dBc/Hz is good enough for SAW-less operation.

Analytical design of a 0.5V 5GHz CMOS LC-VCO

A low-voltage complementary cross-coupled differential LC-VCO was investigated using simple modeling. The bias-controllability of the VCO provides a simple design for low-voltage operation. An analytical design approach realized a 5GHz VCO under a 0.5V supply voltage using a 90-nm digital CMOS process.

A 1.0 V, 2.5 mW, transformer noise-canceling UWB CMOS LNA

We present a transformer noise-canceling ultra-wideband (UWB) CMOS LNA based on a common-gate topology. A transformer, composed of an input inductor and shunt peaking inductor, partly cancels the noise originating from a common-gate transistor. The combination of the transformer with an output series inductor provides wideband input impedance matching. The LNA, implemented with 90-nm digital CMOS technology occupies 0.10 mm2 and achieves S11 Lt -10 dB, NF Lt 3.3 dB, and S21 Gt 7.8 dB across 3.1-10.6 GHz with a power consumption of 2.5 mW from a 1.0-V supply. These results show that the proposed topology is the most suitable for low-power and low-voltage UWB CMOS LNAs.

Small-signal and noise model of fully depleted silicon-on-insulator metal-oxide-semiconductor devices for low-noise amplifier

An RF small-signal and noise model of fully depleted silicon-on-insulator (FD-SOI) metal–oxide–semiconductor field effect transistor (MOSFET) is presented. The model together with its intrinsic model parameters extracted from de-embedding extrinsic parameters reproduces the frequency and noise response of FD-SOI MOSFETs. We have applied the proposed model to a low-noise amplifier (LNA) operating at 5.5 GHz, which is implemented in a 0.15 µm FD-SOI complementary metal–oxide–semiconductor (CMOS) technology. The simulated small-signal and noise performance of the LNA are in good agreement with the measured data of the fabricated LNA.

A 0.5 V area-efficient transformer folded-cascode low-noise amplifier in 90 nm CMOS

We present a low-voltage transformer folded- cascode CMOS low-noise amplifier (LNA). We reduce the chip area of the LNA by coupling an internal inductor and load inductor, and show the effects of the coupling on the LNA by using analytical expressions. The LNA, implemented with 90-nm digital CMOS technology, occupies 0.21 mm2 and achieves S11 < -10 dB, NF = 2.7 dB, and S21 = 16.8 dB at 4.7 GHz with a power consumption of 1.0 mW from a 0.5 V supply. The proposed LNA can replace the conventional folded-cascode LNA.

Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier

We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-μm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.

Accurate Small-Signal Modeling of FD-SOI MOSFETs

A new small-signal model for fully depleted silicon-on-insulator (FD-SOI) MOSFETs operating at RF frequencies is presented. The model accounts for the non-quasi-static effect by determining model parameters using a curve fitting procedure to reproduce the frequency response of FD-SOI MOSFETs. The accuracy of the model is validated by comparison of S parameters with measured results in the range from 0.2 GHz to 20 GHz.

A low-voltage design of controller-based ADPLL for implantable biomedical devices

A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band is designed. The controller-based loop topology is used to control the phase and frequency for reliable handling of the ADPLL output signal. The digitally-controlled oscillator with the delta-sigma modulator is employed to achieve high frequency resolution. The phase error is reduced by the phase selector with 64-phase signal from the phase interpolator. Fabricated in a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm2. It consumes 840 μW from a 0.7-V supply voltage and has a settling time of 80 μs. The measured phase noise is -114.6 dBc/Hz at 200 kHz offset frequency.

A low-power CMOS programmable frequency divider with novel retiming scheme

We propose a novel pulse-swallow programmable frequency divider with a D flip-flop for retiming. The proposed scheme reduces the critical delay path of the modulus control (MC) signal extending the MC timing margin. This enables the high-speed operation of the divider. Moreover, unlike the conventional retiming structure, the MC signal is set and reset by a single signal triggered reset circuitry to eliminate the unwanted division ratio offset and the possible malfunction of set-reset (SR) latch. Simulation results show that the proposed divider designed in 130-nm CMOS technology consumes 53μW at 1-GHz operation frequency from a 0.7-V supply voltage. The proposed divider achieves the lowest power consumption among the previously reported dividers at GHz operations.

A low-voltage design of digitally-controlled oscillator based on the gm/ID methodology

A low-voltage digitally-controlled oscillator (DCO) utilized in a medical implant communication service (MICS) frequency band is designed. A DCO core operating in sub-threshold region is designed based on the gm/ID methodology for optimization. The oscillation frequency is tuned by digital logic block. Thermometer coder with data-weighted averaging and delta-sigma modulator (DSM) are implemented for frequency tuning. High frequency resolution is achieved by using the DSM. The DCO fabricated in a 130-nm CMOS technology has achieved a phase noise of -115.3 dBc/Hz at 200 kHz offset frequency with tuning range of 382 MHz to 412 MHz for the MICS band. It consumes 840 μW from a 0.7-V supply voltage and has a high frequency resolution of 18 kHz.