Jungnam Bae

A low-voltage design of controller-based ADPLL for implantable biomedical devices

A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band is designed. The controller-based loop topology is used to control the phase and frequency for reliable handling of the ADPLL output signal. The digitally-controlled oscillator with the delta-sigma modulator is employed to achieve high frequency resolution. The phase error is reduced by the phase selector with 64-phase signal from the phase interpolator. Fabricated in a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm2. It consumes 840 μW from a 0.7-V supply voltage and has a settling time of 80 μs. The measured phase noise is -114.6 dBc/Hz at 200 kHz offset frequency.

A low-voltage design of digitally-controlled oscillator based on the gm/ID methodology

A low-voltage digitally-controlled oscillator (DCO) utilized in a medical implant communication service (MICS) frequency band is designed. A DCO core operating in sub-threshold region is designed based on the gm/ID methodology for optimization. The oscillation frequency is tuned by digital logic block. Thermometer coder with data-weighted averaging and delta-sigma modulator (DSM) are implemented for frequency tuning. High frequency resolution is achieved by using the DSM. The DCO fabricated in a 130-nm CMOS technology has achieved a phase noise of -115.3 dBc/Hz at 200 kHz offset frequency with tuning range of 382 MHz to 412 MHz for the MICS band. It consumes 840 μW from a 0.7-V supply voltage and has a high frequency resolution of 18 kHz.