Ikkyun Jo

An offset distribution modification technique of stochastic flash ADC

A new non-linearity reduction technique for stochastic flash ADC (SF-ADC) is proposed, focusing on distribution of comparator inputreferred offsets. The SF-ADC test chip fabricated in a 130-nm CMOS process demonstrated the proposed technique can improve SNDR. In addition, the digital re-quantization also can improve the linearity more, where quantization level and fractional correction can be optimized using genetic algorithm.

Design of triple-band CMOS GPS receiver RF front-end

This letter describes the design of a triple-band Global Positioning System (GPS) receiver that simultaneously covers the L1, L2 and L5 frequency bands. The proposed receiver uses an imagerejection technique that can separate signals from the three frequency bands to three corresponding ports. It uses a single RF path containing a low-noise amplifier (LNA), and active and passive mixers with a pair of local oscillator signals. The triple-band GPS RF front-end chip is fabricated using 130 nm CMOS technology, and has a noise figure of less than 7.1 dB and an S11 coefficient of less than −10 dB in the frequency range 1.15-1.6 GHz. The experimental results demonstrate a 35-40 dB image rejection ratio at each output port with a power consumption of 7.2 mW (LNA and mixers) using a 1.2 V supply voltage.

A low-voltage design of controller-based ADPLL for implantable biomedical devices

A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band is designed. The controller-based loop topology is used to control the phase and frequency for reliable handling of the ADPLL output signal. The digitally-controlled oscillator with the delta-sigma modulator is employed to achieve high frequency resolution. The phase error is reduced by the phase selector with 64-phase signal from the phase interpolator. Fabricated in a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm2. It consumes 840 μW from a 0.7-V supply voltage and has a settling time of 80 μs. The measured phase noise is -114.6 dBc/Hz at 200 kHz offset frequency.

A low-power CMOS programmable frequency divider with novel retiming scheme

We propose a novel pulse-swallow programmable frequency divider with a D flip-flop for retiming. The proposed scheme reduces the critical delay path of the modulus control (MC) signal extending the MC timing margin. This enables the high-speed operation of the divider. Moreover, unlike the conventional retiming structure, the MC signal is set and reset by a single signal triggered reset circuitry to eliminate the unwanted division ratio offset and the possible malfunction of set-reset (SR) latch. Simulation results show that the proposed divider designed in 130-nm CMOS technology consumes 53μW at 1-GHz operation frequency from a 0.7-V supply voltage. The proposed divider achieves the lowest power consumption among the previously reported dividers at GHz operations.

A low-voltage design of digitally-controlled oscillator based on the gm/ID methodology

A low-voltage digitally-controlled oscillator (DCO) utilized in a medical implant communication service (MICS) frequency band is designed. A DCO core operating in sub-threshold region is designed based on the gm/ID methodology for optimization. The oscillation frequency is tuned by digital logic block. Thermometer coder with data-weighted averaging and delta-sigma modulator (DSM) are implemented for frequency tuning. High frequency resolution is achieved by using the DSM. The DCO fabricated in a 130-nm CMOS technology has achieved a phase noise of -115.3 dBc/Hz at 200 kHz offset frequency with tuning range of 382 MHz to 412 MHz for the MICS band. It consumes 840 μW from a 0.7-V supply voltage and has a high frequency resolution of 18 kHz.

RF front-end architecture for a triple-band CMOS GPS receiver

This paper describes a triple-band global positioning system (GPS) receiver that simultaneously covers the L1, L2, and L5 frequency bands. The proposed receiver uses an image-rejection technique that can separate signals from the three frequency bands to three corresponding ports. It uses a single RF path containing a low-noise amplifier (LNA), and active and passive mixers with a pair of local oscillator signals. A triple-band GPS RF front-end chip was fabricated using 130nm CMOS technology. The noise figure of this chip is less than 7dB and its S11 coefficient is less than - 10 dB in the 1.15-1.6GHz frequency range. The power consumption of the LNA and mixers is 7.2mW when using a 1.2V supply voltage. The image-rejection ratio (IMRR) between L1 and the other (L2 and L5) band signals is 40dB, while that between the L2 and L5 signals is 37-38dB. To improve the IMRR between the L2 and L5 signals, we investigated the utilization of a digital compensation technique. This technique was confirmed to have improved the IMRR by about 12dB.