Takao Uehara

Optimal Layout of CMOS Functional Arrays

Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design automation systems.

Design and Verification of Large-Scale Computers by Using DDL

This paper describes the total support system for DDL which has been approved by design engineers at Fujitsu. A simulator is used not only at register transfer level but also with gate level description. The translator generates gate level designs which are then optimized by designers. The verifier has powerful functions to detect conflicts in specification and its implementation.

A CAD System for Logic Design Based on Frames and Demons

A hierarchical logic design system based on frames and demons is proposed in this paper. Featuring a graphic editor which puts the design information into frames and a symbolic simulator which consists of demons (data-driven functions stored in frames), the system is flexible enough for a designer to easily add his own functions, such as monitoring functions of design constraints.

A Knowledge-Based Logic Design System

Our computer-aided logic design system employs a synthesizer, a typical knowledgebased system. The register-transfer-level design is described in digital system design language (DDL). The DDL translator generates a technology-independent functional design from the DDL description, and the syntehsizer transforms the functional design into a technology-dependent gate-level design. We implemented the synthesizer as a knowledge-based system because it works without an established algorithm and is easy to modify according to the target technology. Our knowledge-based synthesizer for TTLICs generated a logic diagram of almost as high quality as one designed by a human expert. Only two CPU seconds are required for the FACOM M-380 to generate logic diagrams containing 1000 gates, whereas a human designer takes one week. The CMOS gate array version was developed in only one-half man-year, compared to four man-years for the original version

A Verification Technique for Hardware Designs

Most existing hardware design verification techniques (logic simulation, symbolic simulation etc.), as well as the design phase, are rather synthetic. This paper discusses an analytic verification technique with examples of its application. This technique employs backward symbolic simuation, or causality tracing, which is carried out from the negation of a proposition which should be verified. Analyticity this technique has, not only makes verification powerful but gives it another feature, design error diagnosis.

Logic circuit synthesis using Prolog

This paper briefly reviews the current use of CAD in logic design, and then describes an expert system used to synthesize logic circuits. Specialized knowledge dealing with standard TTL ICs is written in Prolog and AGE, and the results are compared.

An Interactive Logic Synthesis System Based upon AI Techniques

This paper proposes an interactive logic synthesis system which supports translation from behavioral to gate level. A designs specification described in the register transfer language DDL is translated into abstract objects. They are converted to macros representing logical structure and serving as technology independent goals which guide designers in synthesis phases. The system has knowledge about the technology adopted and can accommodate various know-how and design constraints to support the designers tasks of PCB partition and logic synthesis. As a result, it greatly relieves designers from tedious tasks and makes it possible to explore alternative designs.