Nobuaki Kawato

Evaluation and improvement of Boolean comparison method based on binary decision diagrams

R.E. Bryant proposed a method to handle logic expressions (IEEE Trans. Comp., vol.25, no.8, p.667-91, 1986) which is based on binary decision diagrams (BDD) with restriction; variable ordering ix fixed throughout a diagram. The method is more efficient than other methods proposed so far and depends heavily on variable ordering. A simple but powerful algorithm for variable ordering is developed. The algorithm tries to find a variable ordering which minimizes the number of crosspoints of nets when the circuit diagram is drawn. This is applied to the Boolean comparison of ISCAS benchmark circuits for test pattern generation. The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times (or more) faster than times reported in the literature. Some techniques for circuit evaluation ordering are also mentioned.<<ETX>>

Design and Verification of Large-Scale Computers by Using DDL

This paper describes the total support system for DDL which has been approved by design engineers at Fujitsu. A simulator is used not only at register transfer level but also with gate level description. The translator generates gate level designs which are then optimized by designers. The verifier has powerful functions to detect conflicts in specification and its implementation.

A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator

A method is presented to accelerate test generation, which synthesizes a test-generation circuit S(C, F) that combines the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test patterns are generated by searching the inputs to expose faults to the outputs using an ultrahigh-speed simulator (SP).<<ETX>>

A CAD System for Logic Design Based on Frames and Demons

A hierarchical logic design system based on frames and demons is proposed in this paper. Featuring a graphic editor which puts the design information into frames and a symbolic simulator which consists of demons (data-driven functions stored in frames), the system is flexible enough for a designer to easily add his own functions, such as monitoring functions of design constraints.

Logic simulation system using simulation processor (SP)

A special-purpose logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices are described. The system can evaluate a logic circuit containing 4 million logic primitives and 32 Mbytes of memory at a maximum speed of 800 million active primitive evaluations per second. An outline is given of the hardware architecture, and a software system that optimizes hardware performance is discussed.<<ETX>>

A Verification Technique for Hardware Designs

Most existing hardware design verification techniques (logic simulation, symbolic simulation etc.), as well as the design phase, are rather synthetic. This paper discusses an analytic verification technique with examples of its application. This technique employs backward symbolic simuation, or causality tracing, which is carried out from the negation of a proposition which should be verified. Analyticity this technique has, not only makes verification powerful but gives it another feature, design error diagnosis.

Logic circuit synthesis using Prolog

This paper briefly reviews the current use of CAD in logic design, and then describes an expert system used to synthesize logic circuits. Specialized knowledge dealing with standard TTL ICs is written in Prolog and AGE, and the results are compared.

An Interactive Logic Synthesis System Based upon AI Techniques

This paper proposes an interactive logic synthesis system which supports translation from behavioral to gate level. A designs specification described in the register transfer language DDL is translated into abstract objects. They are converted to macros representing logical structure and serving as technology independent goals which guide designers in synthesis phases. The system has knowledge about the technology adopted and can accommodate various know-how and design constraints to support the designers tasks of PCB partition and logic synthesis. As a result, it greatly relieves designers from tedious tasks and makes it possible to explore alternative designs.

A Rule-Based Logic Circuit Synthesis System for CMOS Gate Arrays

This paper presents a CMOS gate-array version of Digital System Design Language/Synthesis eXpert (DDL/SX), a rule-based system for logic circuit synthesis. The system inputs technology-independent functional diagrams, and automatically generates conventional technology-dependent logic diagrams in order to eliminate time-consuming and error-prone tasks in logic design. Because the synthesis process was not clear enough to establish a fixed algorithm, a rule-based approach was adopted to develop the system. This approach made it easy to incrementally improve the systems capabilities by adding, modifying, or deleting design knowledge represented as rules. Experimental use of the system revealed that the automatically generated logic design is almost as good as a manual design, and the design time is reduced by a factor of four.

A high-speed test-generation method using a test generation circuit

This paper discusses the test-generation circuit which automatically generates a test pattern for a combinational circuit. The test-generation circuit is designed so that two algorithms of automatic test generation and fault simulation can be executed by the circuit. The test pattern for the circuit under test is generated at a high speed by simulating the operation of the test-generation circuit using the dedicated logic simulation machine SP. As a result of performance evaluation for the well known benchmark circuits, the test-generation circuit was constructed with eleven times the number of SP elements on the average compared with the circuit under test. By a simulation using only one SP processor, the operation of the test-generation circuit could be simulated at 6 kHz on the average. Thus, it is seen that the test pattern for the circuit under test can be generated with a high fault coverage with a speed surpassing the software on a large-scale computer. The method proposed herein is to apply effectively the architecture of the dedicated machine for a high-speed logic simulation to the search problem such as test generation. Thus, the validity of the idea was verified.