Aritoshi Sugimoto

A new defect distribution metrology with a consistent discrete exponential formula and its applications

We have proposed a novel discrete exponential distribution function, which describes a defect count distribution on wafers or chips more accurately, especially in near defect-free conditions. The conventional approach based on a gamma probability density function (g-pdf) is known to fail in expressing the defects of defect-free wafers or chips, because it always gives zero as the pdf value. Since the number of defects is countable (discrete distribution should be used) and analyzed in terms of nondefective chip yield, the g-pdf cannot be used because of its inaccuracy in the near defect-free condition. A discrete exponential pdf is introduced corresponding to the defect count distribution. In addition, a convolution formula of the new pdf is derived statistically which can express realistic defect count distribution with multiple defect sources. It is noted that the popular negative binomial yield formula (NBYF) is directly derived with the convoluted discrete exponential distribution, which interprets the cluster factor given in NBYF as the number of different defect sources predicted. It is experimentally proven that defect count distributions are approximated by this new model within an average error of about 0.01 defects per wafer from film deposition process data.

An advanced defect-monitoring test structure for electrical screening and defect localization

A new test structure for the detection and localization of short and open defects in large-scale integrated intralayer wiring processes is proposed. In the structure, an open-monitoring element in the first metal layer meanders around lines of short-monitoring elements placed in contact with N-type diffusion regions to make the structure compact. The proposed structure allows defective test structures to be screened through electrical measurements and killer defects to be localized through voltage contrast or optical microscopy methods.

A Discussion on How to Define the Tolerance for Line-Edge or Linewidth Roughness and Its Measurement Methodology

A metrological definition and a target value for linewidth roughness (LWR) in a gate pattern of MOSFETs are proposed. The effects of sampling interval gate-LWR measurements by critical-dimension scanning electron microscopy on measurement accuracy were examined by both experiment and simulation. It was found that a 10-nm interval is sufficiently small to fully characterize roughness in a typically chosen 2-mum-long line. Random image noise and intrinsic LWR variations are found to have larger effects on the measured LWR value than the finiteness of the sampling interval. A practical procedure for improving the measurement accuracy is also devised. Moreover, a methodology for establishing the gate-LWR target is proposed. Threshold-voltage shift caused by gate-LWR is determined from the LWR spectrum and the I-V curves of a transistor without LWR (i.e., ideal I-V curves).

Repair yield simulation with iterative critical area analysis for different types of failure

We propose a general method for repair yield estimation based on critical area analysis using a commercial Monte-Carlo simulator. We classify failures into several types according to the repair rules and use iterative critical area analysis for each type of failure (ICAA-ETF) to calculate the repair yield. Our proposed method makes it possible to accurately estimate within a few hours the repair yield of a memory product. An example of application to an actual SRAM product is discussed to illustrate in detail how our method can be used for critical area calculation and repair yield modeling.

Analysis for effects of mask defects to resist pattern using a three‐dimensional photolithography simulator

A three‐dimensional (3D) photolithography simulator was developed which is composed of the two‐dimensional (2D) mask aerial image simulator, simulator for 2D intensity pattern in aligner (STIPAL), and the 3D resist image simulator, resist process 3D simulator (RESPROT). STIPAL can calculate the mask aerial image in projection printing considering lens aberrations and reticle defects which are very important factors influencing submicron pattern transfer, in addition to the parameters of lens NA (numerical aperture), source wavelength λ, partial coherency σ and defocusing. RESPROT can simulate the 3D resist image in a conventional resist process and contrast enhancement lithography (CEL) using the mask aerial image data calculated by STIPAL. Resist pattern printability or fidelity in the submicron process can be analyzed by these simulators. Resist linewidth shifts caused by reticle defects and lens aberrations were analyzed. Effects of a dark defect (a surplus pattern) or a clear defect (a lack of pattern...

Discrimination of clustered defects on wafers using statistical methods

This paper presents a method for discrimination of clustered defects. The histogram of the number of defects per die is approximated to several major distributions. As a result, we found that Poisson distribution is almost equivalent to real data. The advantage of this method is that accurate coordinates are not required. Therefore it can be applied for almost all tools regardless of their accuracy of coordinates.

New particle-inspection system for CMP-planarization-processed metal layers

With the application of chemical mechanical polishing (CMP), particles become the main defect mode among the various modes of defects. Therefore, particle control becomes increasingly important. For the effective particle control, we need to control not only the number of defects but also the size of defects. However, a conventional particle inspection system using laser scattering could not obtain the information of the accurate particle size. We have developed the new system which can obtain the information of accurate particle size by using image processing. The particle size measured by the new system well agrees with the size measured by SEM. With the new system, we can operate the killer particle control effectively.

Observation of subsurface structures using high-energy SEM

Manufacturing integrated devices with faster clock speeds requires the fine control of three-dimensional gate structures, including line-edge roughness, sidewall angles, and sidewall structures, as well as the control of line widths. In addition, a way to observe underlying structures in devices with multi-layer interconnects is required. As a way to meet future metrology requirements, we propose the use of high-energy scanning electron micrscopy (SEM), which is better suited to the measurement of 3-D structures and underlying structures than conventional low-energy SEM. High-energy SEM is shown to reveal subsurface structures that are not detected by low-energy SEM. Firstly, a motched gate structure and a polycide gate with a sidewall spacer are observed with spatial resolutions of a few nanometers. The relationship between the thickness of the upper layer and beam energy at which underlying structures are observable is also investigated. The beam should be energetic enough to pass through the upper layer without being broadened, but weak enough that incident electrons are back-scattered by the underlying structures. We were able to observe line structures at depths of up to 800 nm by using incident beams with energy levels from 50 to 100 keV.

Advanced surface inspection techniques for SOI wafers

In this paper, it is described that (1) Various type of SOI wafers have each optimum laser illumination mode, (2) Using this optimum laser illumination, 0.1 - 0.3 micrometer particle detection sensitivity has been achieved. (3) By measuring the noise element of scattered light from SOI surface, failure mode can be determined. The performance of the particle detection for each type of wafer and the result of surface roughness failure is also discussed.

Killer defects control on patterned wafers for the sub quarter micron interconnect formation process

Statistical yield modeling has become very practical and effective for defect control since CMP was first applied to the multilevel metallization process in order to achieve surface planarity. This paper presents a study of the defect size to be controlled for the sub-quarter micron interconnect formation process with CMP planarization by estimating the statistical model parameters from experimental data. First, the size distribution, F(x)=ax/sup b/, of defects on PVD processed wafers is obtained. Secondly, the defect sensitivity on sub-quarter micron line and space patterns is estimated. Thirdly, the killer probability during the interconnect formation process is calculated. Finally, we discuss the detection sensitivity of automatic inspection tools for patterned wafers to control killer defects for the sub-quarter micron interconnect formation process.