Takashi Nagano

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

Abstract This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k

4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAM

In recent years, the performance of cellphone cameras has improved, and is becoming comparable to that of SLR cameras. However, the big difference between cellphone cameras and SLR cameras is the distortion due to the rolling exposure of CMOS image sensors (CISs) because cellphone cameras cannot have a mechanical shutters [1]. In addition to this technical problem, the demands for high quality in dark situations and for movies are increasing. Frame-level signal processing can solve these problems, but previous generations of CIS could not achieve both high-speed readout and accessible I/F speed. This paper presents 3-layer-stacked back-illuminated CMOS Image Sensor (3L-BI-CIS) with mounted DRAM as the frame memory.

A 4.1Mpix 280fps stacked CMOS image sensor with array-parallel ADC architecture for region control

A 4.1Mpix 280fps stacked CMOS image sensor with array-parallel ADC architecture is developed for region control applications. The combination of an active reset scheme and frame correlated double sampling (CDS) operation cancels Vth variation of pixel amplifier transistors and kTC noise. The sensor utilizes a floating diffusion (FD) based back-illuminated (BI) global shutter (GS) pixel with 4.2e-rms readout noise. An intelligent sensor system with face detection and high resolution region-of-interest (ROI) output is demonstrated with significantly low data bandwidth and low ADC power dissipation by utilizing a flexible area access function.