Takatoshi Yasui

Deep-submicrometer large-angle-tilt implanted drain (LATID) technology

Deep-submicrometer large-angle-tilt implanted drain (LATID) technology is described. It is found by Monte Carlo process simulation and SIMS measurements that a sufficiently long n/sup -/ region can be formed under the gate by taking advantage of large-angle-tilt implant and successfully without ion channeling by taking care of the implant direction. A design that offsets the n/sup +/ implant by sidewall spacers to suppress the n/sup +/-gate overlap to zero while keeping the n/sup -/ region fully overlapped with the gate is found to be crucial for improved performance and reliability. The device performance, such as current drivability and short-channel effects, is described, and the circuit speed is investigated. Hot-carrier effects such as lateral electric field and device lifetime over a wide range of drain structures are also investigated. The tradeoff between device performance and hot-carrier reliability in deep-submicrometer LATID FETs is discussed. >

Suppression of leakage current in SOI CMOS LSIs by using silicon-sidewall body-contact (SSBC) technology

This paper clarifies two SOI-specific leakage components, STI-induced punchthrough and gate-oxide leakage, found especially in large-scale integration, and proposes a new SOI technology: silicon-sidewall body-contact (SSBC). Without layout penalty and process complexity, SSBC realizes self-aligned body contact to the substrate, which suppresses gate-oxide leakage, and prevents the SOI body from being mechanically stressed, thus eliminating punchthrough leakage. SSBC is promising for scaled SOI CMOS LSIs.