Ichiro Nakao
Panasonic
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Featured researches published by Ichiro Nakao.
international electron devices meeting | 1987
G. Fuse; Hisashi Ogawa; K. Tateiwa; Ichiro Nakao; Shinji Odanaka; M. Fukumoto; Hiroshi Iwasaki; Takashi Ohzone
We develop a new vertical-trench isolation method that utilizes a thin SiO2film in-between double photoresists for uniform top-resist coating and for an etch-back barrier, a poly-silicon film above active regions for an etch-back buffer and large tilt-angle boron ion implantations into the trench-sidewalls for narrow channel effect control. The Planarization with the Resist / Oxide / Resist and the Poly _Silicon (PRORPS) can isolate the whole surface of a 6 inch-diameter wafer very uniformly with a large process margin. The standard deviation of the threshold voltage of a n-channel MOS-FET (W/L= 10µm/0.8µm) over the whole wafer is 0.38 % at about 0.6 V threshold voltage. The narrow-channel-effect is controlled for FETs down to 0.5 µm channel width. The method is applied to the megabit SCC (Surrounded Capacitor Cell) DRAM developed here and the cells and the peripheral-circuits are isolated at the same time successfully.
Archive | 1995
Toshiki Mori; Ichiro Nakao; Tsutomu Fujita; Reiji Segawa
Archive | 1996
Hisakazu Kotani; Hironori Akamatsu; Ichiro Nakao; Toshio Yamada; Akihiro Sawada; Hirohito Kikukawa; Masashi Agata; Shunichi Iwanari
Archive | 2001
Ichiro Nakao; Yoshikatsu Ito
Archive | 1998
Ichiro Nakao; Mariko Takenouchi; Saki Takakura; Satoshi Emura
Archive | 1996
Ichiro Nakao; Mariko Takenouchi; Saki Takakura; Satoshi Emura
Archive | 2000
Yoshikatsu Ito; Ichiro Nakao
Archive | 1995
Mariko Takenouchi; Satoshi Emura; Saki Takakura; Ichiro Nakao
Archive | 1996
Yasushi Okuda; Takashi Hori; Ichiro Nakao
Archive | 1995
Hisakazu Kotani; Hironori Akamatsu; Ichiro Nakao; Toshio Yamada; Akihiro Sawada; Hirohito Kikukawa; Masashi Agata; Shunichi Iwanari