Takayuki Onishi

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level

This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. This architecture consists of triple encoding cores, a decoding core, a multiplexer/de-multiplexer core, and several dedicated application-specific hardware modules with a hierarchical flexible communication scheme for high-performance data transfer. VASA is the worlds first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multi-chip configuration. The VASA implements MPEG-2 video and system CODEC with generic audio CODEC interfaces. An LSI incorporating the architecture was successfully fabricated using the 0.13 /spl mu/m eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multi-view/-angled live TV applications with a multi-chip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.

An H.264/AVC High422 profile and MPEG-2 422 profile encoder LSI for HDTV broadcasting infrastructures

An H.264/AVC encoder LSI (named SARA/E) that supports High422 profile, as well as 422 profile of MPEG-2, has been developed for HDTV broadcasting infrastructures. It contains 257GOPS motion estimation and compensation (ME/MC) engines with search ranges of -271.75 to +199.75 (H) /-109.75 to +145.75 (V), which can utilize almost all H.264/AVC ME/MC tools, multiple reference frame, variable block size, 1/4-pel prediction, macroblock adaptive field/frame prediction, temporal/spatial direct mode, and weighted prediction. Our evaluations show that it can encode fast moving scenes with 1.2 to 1.7 dB higher than the JM. It was successfully fabricated in a 90 nm 9level metal CMOS technology. It integrates 140 million transistors.

Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level

This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. VASA is the worlds first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multichip configuration. An LSI was successfully fabricated using the 0.13-mum eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multiview/-angled live TV applications with a multichip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.

New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex codec LSI

This paper describes a new set-top box of interactive visual communication for home entertainment exploiting single-chip MPEG-2 CODEC LSI. The set-top box has been designed to achieve recent audio-visual compression technologies for consumer applications, especially very-low-delay and robust-error-tolerant dedicated to interactive visual communication. This set-top box with home television set provides standard-TV-quality bi-directional video transmission via commercially available FTTH-based IP broadband network.

A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level

This paper proposes a distributed stream multiplexing architecture for CODEC LSIs with multi-chip configuration, and demonstrates its scalability and usefulness. It consists of each media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip output at the end of the chain. Dispensing with external stream handling devices contributes to both high throughput and downsizing. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV channels. The architecture was implemented in a fabricated single-chip MPEG-2 422P@HL CODEC LSI and showed a good performance on an evaluation board system.

MVC real-time video encoder for full-HDTV 3D video

3D video technologies such as 3D cameras, displays, and video-processing have become more important for achieving high quality and immersive video services. We propose an H.264 MVC encoder architecture for real-time 3D video distribution and transmission. We also present the first-ever successful development of a full-HDTV real-time MVC encoder.

A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems

This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 1080I decoding core, an audio DSP, a RISC, and a multiplexer/de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 3.8 million transistors on a 9.7 mm/spl times/9.7 mm die using the 0.13 /spl mu/m seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 1080I decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.

Single-chip 4K 60fps 4:2:2 HEVC video encoder LSI with 8K scalability

This paper proposes the worlds first single-chip 4K 60fps 4:2:2 HEVC video encoder LSI (named “NARA”) with 8K scalability for broadcasting with professional high image quality. It consists of a prediction core with a new prediction mode decision framework, dual coding cores, controlling RISCs, and high speed data buses with multichip 8K configuration, using 28nm CMOS technology. The NARA LSI will lead to a new dimension in future high-quality 8K world.

A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K

This paper describes a new 120 fps (frames per second) real-time HEVC encoder for higher frame rate video encoding and transmission. Modification in the flexible customizable software architecture of encoder LSIs makes it possible to achieve the temporally scalable HEVC encoding with upward compatibility for existing 60 fps-based systems. The encoder also achieves 4K/120fps video encoding in real time through the synchronized operation of multiple 2K/120fps encoders working in parallel. The proposed encoder systems will open the door to the next generation high frame rate UHDTV services.

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

This paper proposes a distributed stream multiplexing architecture for video codec LSIs with multi-chip configuration. This distributed architecture utilizes a built-in media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip stream output at the end of the chain. Dispensing with external post-processing devices contributes to both high throughput and downsizing of high-end video codec systems. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV programs. The architecture was successfully implemented in a fabricated single-chip MPEG-2 422P@HL codec LSI and utilized for the development of a super high-resolution video codec system.