Takeaki Sugimura

Development of a High Speed Vision System for Mobile Robots

In order to achieve human-like quick eye movements and image processing for intelligent mobile robots, a high speed vision system is developed. The vision system is composed of a binocular camera head and high speed image sensors. The camera head is originally designed to mount neuromorphic vision chips fabricated using three-dimensional integration technology. The prototype of the neuromorphic vision chip has three layers: (1) photoreceptor layer, (2) horizontal and bipolar cell layer, and (3) ganglion cell layer. An image sensor is separately developed, which corresponds to the photoreceptor layer of the layered vision chip. The image sensors are tentatively mounted on the camera head, since the resolution of the prototype of the layered vision chip is not sufficient at this stage. The camera head has an azimuth DOF for each eye and a common elevation DOF. The weight of the camera head is strictly limited, since it is mounted on a mobile robot. In order to satisfy both demands for the quick movements and light weight, the camera head is designed based upon a simple parallel mechanism. The total performance of the vision system is examined in this work. Saccadic eye movement and frequency response are experimentally reviewed

Fundamental Study of Complementary Metal Oxide Semiconductor Image Sensor for Three-Dimensional Image Processing System

In this paper, we describe a fundamental study of a complementary metal oxide semiconductor (CMOS) image sensor for a three-dimensional (3D) image-processing system. We proposed a pixel circuit with correlated double sampling (CDS) and high-speed image capturing for high-speed image processing. The CDS and high-speed image-capture circuit should be realized simultaneously to allow high-speed image processing. The pixel circuit can realize CDS and high-speed image-capture functions simultaneously. The CDS and high-speed image capturing are realized by using a pixel sample hold capacitor and shared coupling capacitor. Appending extra capacitors causes the pixel circuit size to become large in the two-dimensional (2D) CMOS image sensor. We proposed a 3D CMOS image sensor that can reduce the pixel circuit size and the electrical wiring length and increase the fill factor, even with CDS and high-speed image capturing. Therefore, small, high-speed parallel-processing systems can be realized by using our 3D CMOS image sensor. We fabricated the prototype 2D pixel circuit with CDS and high-speed image capturing. The prototype pixel circuit is successfully implemented in the simultaneous function. We believe the proposed pixel circuit is very effective for 3D CMOS image processing.

New Reconfigurable Memory Architecture for Parallel Image-Processing LSI with Three-Dimensional Structure

A reconfigurable memory network for a parallel image-processing LSI with a three-dimensional structure is proposed. The proposed memory network can be dynamically configured by changing the connections between processing elements (PEs) and memories in accordance with the required part of the stored image data. In addition, a specification of the data bandwidth between PEs and the proposed memory network can be changed in the synchronization with single instruction stream-multiple data stream (SIMD) and multiple instruction stream-multiple data stream (MIMD) operations. Therefore, data transfer has greater flexibility. Also, from the result of the performance evaluation by implementation into the field programmable gate array (FPGA), it was successfully shown that the proposed memory network reduced the execution time by up to 28.2% for a 9×9 filtering operation.

Quantitative Derivation and Evaluation of Wire Length Distribution in Three-Dimensional Integrated Circuits Using Simulated Quenching

Three-dimensional (3D) integration is the most promising technology to improve IC performance by stacking some active device layers and connecting them using vertical interconnections. In this paper, in order to quantitatively evaluate the benefits of 3D IC, wire length distributions in 3D ICs are derived by adapting the simulated quenching algorithm for 3D placement and routing of specific benchmark circuits. By evaluating the wire length distribution, we can confirm that the total wire length is reduced by 26.0 and 41.3% with three and five active layers, respectively. Similarly, 38.1 and 52.0% reduction in the longest wire length with three and five active layers can be achieved.

Low-Power and High-Sensitivity Magnetoresistive Random Access Memory Sensing Scheme with Body-Biased Preamplifier

In this paper, we describe a new magnetoresistive random access memory (MRAM) sensing scheme with a body-biased preamplifier for low-power and high-sensitivity operation. The proposed new MRAM sense amplifier consists of a current sense preamplifier with a body biasing differential pair of a common-gate amplifier and a voltage sense amplifier. The preamplifier controls bitline voltage appropriately and amplifies the difference in bitline current as current-mode sense amplifier. The new sense amplifier enhances sensitivity, and the body-biased preamplifier enables low-voltage operation. To evaluate the proposed circuit, the modeling of magnetic tunnel junction (MTJ) resistance characteristics was performed with a VHDL-AMS description, and the proposed circuit was simulated with a mixed signal circuit simulator. From the simulation result, it is confirmed that the proposed sensing scheme results in a 1.57 times faster access time than a conventional scheme, and that the power of the sense amplifier is lower than that of the conventional amplifier at the same speed.

Low power spin-transfer magnetoresistive random access memory writing scheme with selective word line bootstrap

We describe a new writing scheme with a selective word line bootstrap for spin-transfer magnetoresistive random access memory (MRAM). Applying spin-transfer switching to MRAM, its writing power consumption decreases and its memory cell area is also reduced. However, during write operation, the required bit line cramp voltage for stored data switching depends on the value of stored data, magnetic tunnel junction (MTJ) characteristics, and switching current direction. Therefore, the bit line voltage must be optimized to minimize the power consumption. With the proposed scheme, word line voltage is varied according to the value of writing data in order to decrease the threshold bit line voltage. Furthermore, the spin-transfer MRAM resistance model with reading and writing operations was successfully implemented for the circuit simulation. From the simulation results, it was found that writing threshold bit line bias during writing operation can decrease from 17 to 28% with the proposed selective bootstrap. Also, more than 25% of the cell transistor gate width can be decreased. This result shows that the proposed writing scheme is effective in reducing power consumption, and can also reduce the MRAM cell area.

Fabrication and Evaluation of Magnetic Tunnel Junction with MgO Tunneling Barrier

Magnetoresistive random access memory (MRAM) has recently attracted considerable attention due to its non-volatility and high programming speed. A high Tunnel magnetoresistance (TMR) ratio is a key factor of MRAM. However, a conventional MRAM using aluminum oxide as insulator film shows a low TMR ratio of several tens of percents. MgO tunneling insulator is one of the candidates for achieving a high TMR ratio. In this study, we fabricated and evaluated Magnetic tunnel junctions (MTJs) with MgO tunneling barrier on a clad Cu word line.