Takehiko Hojo

A 65nm low-power embedded DRAM with extended data-retention sleep mode

An extended data retention (EDR) sleep mode with ECC and MT-CMOS is proposed for embedded DRAM power reduction. In sleep mode, the retention time improves by 8 times and the leakage current is reduced to 13% of the normal operation mode. Since ECC scrubbing operates only in the EDR sleep mode, read/write performance is not degraded. A 65nm low-power embedded DRAM macro featuring 400MHz operation and 0.39mW of data-retention power is realized

13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current

Battery lifetime is the key feature in the growing markets of sensor networks and energy-management system (EMS). Low-power MCUs are widely used in these systems. For these applications, standby power, as well as active power, is important contributor to the total energy consumption because active sensing or computing phases are much shorter than the standby state. Figure 13.4.1 shows a typical power profile of low-power MCU applications. To achieve many years of battery lifetime, the power consumption of the chip must be kept below 1μA during deep sleep mode. Another key feature of a low-power MCU for such applications is fast wake-up from deep-sleep mode, which is important for low application latency and to keep wake-up energy minimal. For fast wake-up, the system must retain its state and logged information during sleep mode because several-hundred microseconds are needed for reloading such data to memories. Conventional SRAM consumes much higher retention current than the required deep-sleep-mode current as shown in Fig. 13.4.1. Embedded Flash memories have limited write endurance on the order of 105 cycles making them difficult to use in applications that frequently power down. Embedded FRAM [1,2] has been used for this purpose and it could be used as a random-access memory as well as a nonvolatile memory. However, as a random-access memory, its slow operation and high energy consumption [1,2] limits performance of the MCU and battery lifetime. Furthermore, additional process steps for fabricating FRAM memory cells increase the cost of MCU. SRAM can operate at higher speed with lower energy without additional process steps, but high retention current makes it difficult to sustain data in deep-sleep mode. To solve this problem, we develop low-leakage current SRAM (XLL SRAM) that reduce retention current by 1000× compared to conventional SRAM and operate with less than 10ns access time. The retention current of XLL SRAM is negligible in the deep-sleep mode because it is much smaller than the amount of the deep-sleep-mode current of MCU, which is dominated by active current of the real-time clock and control logic circuits. By using XLL SRAM, the store and reload process during mode transitions can be eliminated and wake-up time from deep-sleep mode of MCU is reduced to few microseconds. This paper describes a 128kb SRAM with 3.5nA (27fA/b) retention current, 7ns access time, and 25μW/MHz active energy consumption. Its low retention current, high-speed, and low-power operation enable to activate SRAM in the deep-sleep mode, and also provides fast wake-up, low active energy consumption and high performance to MCU.

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications

Embedded DRAMs have superior features for applications that require very high memory bandwidth, such as graphics and multimedia. To achieve high memory bandwidth, various techniques such as widening input/output pins shrinking the unit array size, and performing a read operation and a write operation concurrently have been reported. However, these embedded DRAM macros incur considerable area penalty to obtain high memory bandwidth. Among the techniques for achieving high bandwidth, the concurrent read/write operation is a very effective method in performing a read-modify-write function and a double-buffer function for the graphics applications. A pseudo-two-port embedded DRAM macro that performs concurrent read/write operations at high frequency without sacrificing cell efficiency is reported in this paper. To accomplish this, a read/write cross-point switch circuit (RWCC) and distributed steering redundancy switches (DSRS) are introduced. A 32 Mb macro is characterized via a test-chip fabricated in a 65 nm embedded DRAM process.

A DRAM module generator with an expandable cell array scheme

This paper describes a DRAM module generator (DRAMGen) with an expandable cell array scheme. DRAMGen uses a modularization scheme. This expandable cell array scheme uses the cell array segment as the unit of increment and applies shared sense-amplifier scheme. This scheme reduces the area penalty to less than five percent and has little performance penalty. Using a 0.35 /spl mu/m process technology, a series of DRAM macros with flexible bank, row, column, and I/O-bit configurations consequently produce 2112 derivatives. The module generator has successfully generated a number of macros, taking five seconds for each macro, including a 32 Mb macro with a 150 MHz cycle time.

Interface socket design methodology to generate embedded DRAM macros

A new design methodology for embedded DRAM is introduced. The DRAM macro consists of common DRAM core and interface socket. Splitting the DRAM macro into common DRAM core and interface socket widens the reconfigurability of the functions of the macro. An experimental chip consists of 12M-bit DRAM core and synchronous interface socket was developed with 0.18 /spl mu/m technology.