Hitoshi Iwai

A 65nm low-power embedded DRAM with extended data-retention sleep mode

An extended data retention (EDR) sleep mode with ECC and MT-CMOS is proposed for embedded DRAM power reduction. In sleep mode, the retention time improves by 8 times and the leakage current is reduced to 13% of the normal operation mode. Since ECC scrubbing operates only in the EDR sleep mode, read/write performance is not degraded. A 65nm low-power embedded DRAM macro featuring 400MHz operation and 0.39mW of data-retention power is realized

Cantilever type probe card for at-speed memory test on wafer

In this paper, we present a new low cost probe card, which enables high speed (500 MHz) memory test on wafer. Since it is difficult to characterize memory devices on wafer at high speed with a low cost probe card, then high speed memory test is usually conducted after assembling packages, although package test requires long lead time for test. We have tested Embedded DRAM at 500 MHz on wafer with the new probe card which has Cantilever needles. The results show that the probe card can be used for memory at-speed test up to 500 MHz.

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications

Embedded DRAMs have superior features for applications that require very high memory bandwidth, such as graphics and multimedia. To achieve high memory bandwidth, various techniques such as widening input/output pins shrinking the unit array size, and performing a read operation and a write operation concurrently have been reported. However, these embedded DRAM macros incur considerable area penalty to obtain high memory bandwidth. Among the techniques for achieving high bandwidth, the concurrent read/write operation is a very effective method in performing a read-modify-write function and a double-buffer function for the graphics applications. A pseudo-two-port embedded DRAM macro that performs concurrent read/write operations at high frequency without sacrificing cell efficiency is reported in this paper. To accomplish this, a read/write cross-point switch circuit (RWCC) and distributed steering redundancy switches (DSRS) are introduced. A 32 Mb macro is characterized via a test-chip fabricated in a 65 nm embedded DRAM process.

Low power embedded DRAM using 0.6V super retention mode with word line data mirroring

An 88% reduction of refresh power of the 65nm embedded DRAM is achieved using Super Retention Mode (SRM) with Word Line Data Mirroring(WLDM). The retention time in Super Retention Mode is measured in the range of 0.55V to 1.2V. The minimum refresh power is obtained at 0.6V. The retention time of Super Retention Mode at 0.6V is extended by 4.1 times from that of conventional single cell operation at 1.2V. The transition time from normal mode to Super Retention Mode of 22.6μs is achieved with only 0.4% area penalty.