Takehisa Hayashi

Power Efficient Approach and Performance Control for Routers

We introduce two approaches for power saving routers, which are the power efficient designing and the power saving designing. Power efficient designing enables a high performance router at low power consumption. As a part of power efficient designing, we have integrated ASICs/FPGAs of routers and developed a scalable central architecture. Additionally, we used new high speed memories and high speed interfaces such as a SerDes. As a result, the whole power consumption of our router adopting power efficient designing was reduced over 50% compared to conventional routers. Power saving designing is an approach to cut down wasted power consumption. Two major aspects belong to power saving designing, which are static performance control and dynamic performance control. We have been studying on static performance control, such as power cutting technology per port or module, and power saving mode by frequency switching. We were successful in saving 10-20% of power compared to conventional routers using this power saving mode by frequency switching. Furthermore, we introduce the dynamic performance control as a promising power saving approach for next generation routers. The router controls its performance dynamically according to the amount of received traffic. We show two technologies needed for this approach, which are the dynamically performance controllable router architecture/circuit, and the traffic monitoring/predicting technology. We consider that working on these technologies will save more power.

A novel clock distribution system for CMOS VLSI

A novel all-digital clock distribution system for CMOS VLSI, capable of generating small-skew, four-phase, and non-overlap clock signals when supplied with only a one-phase clock signal, is described. The frequency of the input clock signal can be decreased by 75% without a phase-locked loop (PLL) by adopting this system. The key concept of this system is to extract phase-adjusted multi-phase clock signals from a Multi-tapped Variable Delay Line (MVDL). With the use of a 28-MHz input reference clock, this system has been applied to a 0.8-/spl mu/m CMOS gate array to produce four-phase 28-MHz clock signals with 12.5% duty cycle. Using the measured delay time of the components, clock skew and delay time variations between phases are estimated to be /spl plusmn/0.6 ns and /spl plusmn/0.5 ns, respectively. Both of these values can be decreased to /spl plusmn/0.2 ns with the adoption of an alternative circuit configuration.<<ETX>>

A current-mode column comparator circuit for high-speed, low-power on-chip cache-TAG memories

The authors describe a low-power comparator circuit which is especially useful for on-chip cache-TAG memories. A novel TAG memory comparator circuit scheme, called a current-mode column comparator (CMCC) scheme, is proposed, and the low-power nature of the CMCC without degraded accessing speed is described. An experimental 128-entry by 32-b TAG-memory test chip was fabricated using 0.5-&mu;m BiCMOS technology, and a 3-ns address input to hit delay time was obtained. The power dissipation of the sense amplifiers was reduced by a factor of 10