Akira Yamagiwa

A CPU chip-on-board module

A CPU chip-on-board module for low and midrange computers is described. The module consists of a CPU bare chip, 24 SRAMs packaged in SOJ packages, and some decoupling capacitors. The module substrate is a printed circuit board (PCB) made of bismaleimide-triazine resin. The module (156 mm/spl times/58 mm) consists of four signal metal layers and four power/ground metal layers. A square clearance hole (17 mm/spl times/17 mm) for the CPU is formed in the central part of the PCB. A thermal spreading metal is glued to the PCB from the rear side, covering the square hole, and the CPU chip is die-bonded onto the metal plate. The thermal resistance can be made smaller than 2/spl deg/C/W with 0.4 m/s of wind velocity. Numerical analysis of electrical characteristics of the module shows that it can reduce signal delay time from the CPU to cache memories by 10% compared with that of a daughter board type module with the CPU packaged in a pin-grid array package. It is estimated that simultaneously switched noise can be reduced by 60% from that of the daughter board type module. >

A novel clock distribution system for CMOS VLSI

A novel all-digital clock distribution system for CMOS VLSI, capable of generating small-skew, four-phase, and non-overlap clock signals when supplied with only a one-phase clock signal, is described. The frequency of the input clock signal can be decreased by 75% without a phase-locked loop (PLL) by adopting this system. The key concept of this system is to extract phase-adjusted multi-phase clock signals from a Multi-tapped Variable Delay Line (MVDL). With the use of a 28-MHz input reference clock, this system has been applied to a 0.8-/spl mu/m CMOS gate array to produce four-phase 28-MHz clock signals with 12.5% duty cycle. Using the measured delay time of the components, clock skew and delay time variations between phases are estimated to be /spl plusmn/0.6 ns and /spl plusmn/0.5 ns, respectively. Both of these values can be decreased to /spl plusmn/0.2 ns with the adoption of an alternative circuit configuration.<<ETX>>

Package design for high-speed low-cost ASIC LSIs

Cofired alumina ceramic, alumina-based Cu/polyimide thin films, and plastic PGAs (pin-grid-arrays) are compared in terms of electrical and thermal characteristics and cost. Plastic PGA with the cavity down and a three-layer structure is shown to be the best way to meet the requirement of over 50-MHz signal transmission, thermal resistance and cost. The best results on the 592-pin plastic PGA package and its simulation results are described.<<ETX>>