Takemitsu Kunio

Sub-50-nm physical gate length CMOS technology and beyond using steep halo

Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 /spl mu/A//spl mu/m for an off current of less than 10 nA//spl mu/m at 1.2 V with T/sub ox//sup inv/=2.5 nm. For an off current less than 300 nA//spl mu/m, 33-nm pMOSFETs have a high drive current of 400 uA//spl mu/m. Short-channel effect and reverse short-channel effect are suppressed simultaneously by using the HRR-SA process to activate a source/drain extension (SDE) after forming a deep source/drain (S/D). This process sequence is defined as a reverse-order S/D (R-S/D) formation. By using this formation, 24-nm nMOSFETs are achieved with a high drive current of 800 /spl mu/A//spl mu/m for an off current of less than 300 /spl mu/A//spl mu/m at 1.2 V. This high drive current might be a result of a steep halo structure reducing the spreading resistance of source/drain extensions.

Low-Voltage Switching Characteristics of SrBi2Ta2O9 Capacitors

Ferroelectric capacitor arrays were fabricated using SrBi2Ta2O9 (SBT) thin films. Hysteresis and pulse responses were measured as functions of capacitor size and applied voltage. The remanent polarization (P r) at 5 V does not depend on capacitor size, though P r at low applied voltage decreases considerably as capacitor size decreases below 10 µ m. High-voltage pulse application enhances low-voltage polarization switching. Retention characteristics strongly depend on operating voltage. Switching charge at 2 V or above is stable up to 104 s retention, while that at 1 V operation decreases with increasing retention time.

Characteristics of 0.25 µm Ferroelectric Nonvolatile Memory with a Pb(Zr, Ti)O3 Capacitor on a Metal/Via-Stacked Plug

A 0.25-µm ferroelectric memory with 16 kbit-cell array was fabricated. A Pb(Zr, Ti)O3 (PZT) capacitor was formed on a metal(Al)/via(W)-stacked plug using low temperature metal organic chemical vapor deposition (MO-CVD). The backend process had no effect on the PZT capacitor properties. The 1×1 µm2 capacitor shows good fatigue and imprint endurance. Signal voltage on the bit-line in the cell array is 1.06 V for switching and 0.58 V for unswitching. These results agree well with the pulse-response measurement of the parallel capacitor. However, the signal voltage deviation becomes larger with the capacitor size reduction. The 16 kbit-cell array shows the column access time of 50 ns and the minimum operation voltage of 1.6 V.

Energy levels and degeneracy ratios for chromium in silicon

Abstract The energy levels and the degeneracy ratios for chromium in silicon have been determined by the Hall coefficients which were measured by the van der Pauw method. Using the curve fitting method for carrier concentration based on the charge balance equation with the root mean square deviation, the analysis shows that chromium in silicon gives rise to two donor levels. The energy levels of the upper and lower donors are located at Ec-0.226(±0.010)eV and Ev+0.128(±0.005)eV, and their degeneracy ratios are 1 3 and 1 4 , respectivel

Quarter-Micron Interconnection Technologies for 256-Mbit Dynamic Random Access Memories

Quarter-micron interconnection technologies for 256-Mbit dynamic random access memories (DRAMs) are reviewed. Since the density of memory capacity is increased, both decreasing feature size and increasing sophistication of cell structures are required, resulting in three-dimensional structures. This trend leads us to the introduction of new interconnection technologies which have good coverage, low resistivity and high reliability, because the three-dimensional device structure requires high aspect-ratio contact hole plugs and narrow-pitch metal lines on different surface levels. The state of the art and current problems are discussed for quarter-micron contact-hole filling and quarter-micron interconnection lines.

PHOTOIONIZATION CROSS SECTIONS IN VANADIUM-DOPED SILICON.

Vanadium‐doped silicon has been investigated using a photocapacitance method on n+‐p and p+‐n junctions. The photoionization cross‐section spectra showed two levels at 0.47 eV below the conduction band and 0.485 eV above the valence band, and the complementary optical transition threshold energies were 0.665 and 0.77 eV, respectively. For the Ec−0.47‐eV level, the electron photoionization cross section at the threshold energy depends significantly on temperature. This would be due to the photothermal ionization process via the excited states. For the Ev+0.485‐eV level, the sum of the threshold energies in electron and hole emission processes was greater than the band gap. This indicates that phonon broadening due to lattice relaxation occurs in the photoionization spectrum. According to the configuration coordinate model, the local phonon energy and the lattice relaxation energy are approximately 350 K and 0.13 eV, respectively.

Ultralow resistance W/poly-Si gate CMOS technology using amorphous-Si/TiN buffer layer

Advanced tungsten/pn-poly-Si gate CMOS devices with an ultralow sheet resistance of 1 /spl Omega//sq. have been demonstrated using an amorphous-Si/TiN buffer layer. A low-resistivity tungsten film is formed by large grain size tungsten on an amorphous-silicon (a-Si) film. This result can be explained by the Mayadas-Shatzkes theory. After a source/drain annealing process, W/a-Si/TiN/pn-poly-Si systems become W/WSi/sub x//TiN/pn-poly-Si systems without impurity interdiffusion between the pn-poly-Si gate electrodes. The propagation delay time of a CMOS inverter ring oscillator with this novel gate electrode is considerably smaller than that with a cobalt-salicide film in a wider channel width.

Ultrauniform Chemical Mechanical Polishing (CMP) Using a "Hydro Chuck", Featured by Wafer Mounting on a Quartz Glass Plate with Fully Flat, Water-Supported Surface

For uniform device planarization by chemical mechanical polishing (CMP), the effect of a wafer-chuck structure on the polishing uniformity is examined. It is found that wafer mounting on a r igid plate (WOR) structure is superior to wafer mounting on an elastic film (WOE) structure for diminishing polishing fluctuation near the wafer perimeter. The WOR structure, however, generates abnormally polished spots in the wafer due to abrasive particle inclusion in the region between the rigid chucking plate and the wafer. A new WOR-type wafer chuck, called a hydro chuck, is developed: the chuck is made of a quartz glass plate with a fully flat water-supported surface. Water is continuously supplied on the quartz glass plate to form an aqueous hydro film, which suppresses slurry penetration between the rigid quartz glass plate and the wafer. Using the hydro chuck, an uniformity of ±200 A in a 6 wafer is realized for CVD-SiO2 polishing.

Defect levels in chromium-doped silicon

Abstract The transient capacitance technique has been used to study the chromium-related levels in the silicon band gap. Chromium was diffused at temperature of 1100 and 1150°C for 0.5 and 3 hr. Five different levels at Ec−0.11 eV, Ec−0.21 eV, Ec−0.28 eV, Ec−0.36 eV and Ec−0.45 eV were obtained from the Arrheniu plots of the electron thermal-emission rates. The number of levels in the upper half of the band gap decreased from five to two with an increase of Cr-diffusion period. Two levels were located at Ec−0.20 eV (donor) and Ec−0.43 eV (acceptor). A donor level was also observed at Ev + 0.25 eV. The donor level was not affected by the diffusion condition. The majority carrier capture cross sections of the three dominant levels have been measured by the transient capacitance technique modified by the pulse transformer. The values were σn = 4.1 × 10−15 cm2 for the upper donor at Ec−0.20 eV, σn = 2.0 × 10−16 cm2 for the acceptor at Ec −0.43 eV and σp = 9.1 × 10−18 cm2 for the lower donor at Ev + 0.25 eV, and were independent of temperature. The three dominant levels are due to distinct chromium centers.