Tohru Miwa

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A V/sub dd//2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

This paper describes the circuit technologies and the experimental results for a 1 Mb flash CAM, a content addressable memory LSI based on flash memory technologies. Each memory cell in the flash CAM consists of a pair of flash memory cell transistors. Additionally, four new circuit technologies have been developed: a small-size search sense amplifier; a highly parallel search management circuit; a high-speed priority encoder; and word line/bit line redundancy circuits for higher production yields. A cell size of 10.34 /spl mu/m/sup 2/ and a die size of 42.9 mm/sup 2/ have been achieved with 0.8 /spl mu/m design rules. Read access time and search access time are 115 ns and 135 ns, respectively, with a 5 V supply voltage. Power dissipation in 3.3 MHz operations is 210 mW in read and 140 mW in search access.

A 128 kb FeRAM macro for a contact/contactless smart card microcontroller

For contact/contactless smart-card applications, a ferroelectric RAM (FeRAM) macro must operate with supply voltages ranging from 2.7 V to 5.5 V, as standardized by ISO, and have endurance of more than 10/sup 8/ write/read cycles and memory size flexible from 32 kb to 128 kb. In addition, for contactless smart card applications, low current consumption is essential. This macro meets these requirements using: (1) 3-metal process capacitor-on-metal/via-stacked-plug (CMVP) memory cell; (2) voltage regulation architecture; (3) main/sub bit line and word line structure; and (4) dynamic-type offset sense amplifier.

Characteristics of 0.25 µm Ferroelectric Nonvolatile Memory with a Pb(Zr, Ti)O3 Capacitor on a Metal/Via-Stacked Plug

A 0.25-µm ferroelectric memory with 16 kbit-cell array was fabricated. A Pb(Zr, Ti)O3 (PZT) capacitor was formed on a metal(Al)/via(W)-stacked plug using low temperature metal organic chemical vapor deposition (MO-CVD). The backend process had no effect on the PZT capacitor properties. The 1×1 µm2 capacitor shows good fatigue and imprint endurance. Signal voltage on the bit-line in the cell array is 1.06 V for switching and 0.58 V for unswitching. These results agree well with the pulse-response measurement of the parallel capacitor. However, the signal voltage deviation becomes larger with the capacitor size reduction. The 16 kbit-cell array shows the column access time of 50 ns and the minimum operation voltage of 1.6 V.

A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM

This paper describes two new circuit techniques for nonvolatile SRAMs with back-up ferroelectric capacitors (NV-SRAMs). These circuits are able to overcome the size and low-voltage-reliability problems faced by the original NV-SRAM. A new 0.25-/spl mu/m-design-rule four-metal-layer NV-SRAM cell occupies 9.7 /spl mu/m/sup 2/, that is the same area as a 0.25-/spl mu/m three-metal-layer SRAM cell. A high-voltage/negative-voltage plate line driver allows a low-voltage-operation NV-SRAM array to improve its nonvolatile retention characteristics. A 512 Kbit test macro has also been designed with only one percent area overhead from a conventional SRAM macro.

A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers

For contact/contactless smart-card applications, a ferroelectric RAM (FeRAM) macro must operate with supply voltages ranging from 2.7 V to 5.5 V, as standardized by ISO, and have endurance of more than 10/sup 8/ write/read cycles and memory size flexible from 32 kb to 128 kb. In addition, for contactless smart card applications, low current consumption is essential. This macro meets these requirements using: (1) 3-metal process capacitor-on-metal/via-stacked-plug (CMVP) memory cell; (2) voltage regulation architecture; (3) main/sub bit line and word line structure; and (4) dynamic-type offset sense amplifier.

NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell area overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.

A 1 Mb 5-transistor/bit non-volatile CAM based on flash-memory technologies

A 1 Mb content-addressable memory LSI based on flash technologies (flash CAM) has memory cells consisting of a pair of flash memory cell transistors. 10.34 /spl mu/m/sup 2/ cell and 42.9mm/sup 2/ die are attained with 0.8 /spl mu/m design rules. The flash CAM can be searched for masked binary data. Read access time and search access time are 115 ns and 145 ns, respectively, with a 5 V supply voltage. Power dissipation is 200 mW at 3.3 MHz. The flash CAM cell consists of two floating-gate transistors. This structure is in strong contrast to the comparator-added-storage structure of 17-transistor SRAM-based cells or five-transistor two-capacitor of DRAM-based cells. In addition to non-volatility, flash CAMs also feature on-board programmable/erasable memory.

FeRAM device and circuit technologies fully compatible with advanced CMOS

Recent progress in FeRAM device and circuit technologies that are fully compatible with advanced CMOS logic is described. We have developed a ferroelectric capacitor of a CMVP (capacitor-on-Metal/Via-stacked-Plug) memory cell that is fabricated after the completion of multilevel metallization. A 0.35-/spl mu/m 2T/2C FeRAM macro based on CMVP has been fabricated for smart card applications. The chip features a wide operation voltage range, high write/read endurance, low consumption current, and a flexible memory size. The CMVP technologies also enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile (NV-SRAM: nonvolatile SRAM). The memory cell consists of a six-transistor SRAM cell and two stacked back-up ferroelectric capacitors. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible.

FeRAM retention analysis method based on memory cell read signal voltage measurement

A retention analysis method for ferroelectric random access memory (FeRAM) was developed, in which read signal voltages from memory cells are measured. The method uses on-chip sample/hold circuits, an off-chip A/D converter, and memory large-scale integration testing equipment. FeRAM chip retention lifetime can be estimated on the basis of FeRAM read signal voltages after retention periods of one day and upwards. When used as a tool to estimate long-term data retention in FeRAM chips and to analyze fluctuations in memory cell characteristics, this method can provide useful information about FeRAM reliability.