Hisayuki Shimada

Tantalum-gate thin-film SOI nMOS and pMOS for low-power applications

The threshold voltages of thin-film fully-depleted silicon-on-insulator (FDSOI) nMOS and pMOS have been controlled by employing tantalum (Ta) as the gate materials. Ta-gate FDSOI MOSFETs have excellent threshold voltage control for 1.0 V application on low impurity concentration SOI layers in both nMOS and pMOS. The low-temperature processing after the gate oxidation step leads to good on/off characteristics in Ta-gate SOI MOSFETs because of no reaction between Ta gate electrode and SiO/sub 2/ gate insulator. This technology makes it possible to drastically decrease the number of the process steps for CMOS fabrication, because the same gate material is available for both nMOS and pMOS.

Current drive enhancement by using high-permittivity gate insulator in SOI MOSFET's and its limitation

Speed enhancement effects by using a high-permittivity gate insulator in SOI MOSFETs and its limitation were investigated by a two-dimensional device simulator and circuit simulator. The SOI structure is suitable to have excellent current drive by using a high-permittivity gate insulator. Although the gate capacitance increases as a function of its dielectric constant, the current drive does not increase proportionally due to the inversion capacitance. According to the simulation results of the delay time, when the pulse waveforms driven by a CMOS inverter are propagated through 1 mm-long interconnects, the delay time significantly reduces at a dielectric constant value of around 25 (Ta/sub 2/O/sub 5/). Thus, it is worthwhile using Ta/sub 2/O/sub 5/ for gate insulator to achieve high-speed operation. Furthermore, the reduction of source parasitic series resistance is a key issue to realize the highest current drive by using a high-permittivity gate insulator in SOI MOSFET.

Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing

A reliable tantalum (Ta)-gate device technology, which can drastically reduce the number of process steps, has been developed. Ta-gate fully-depleted-silicon-on-insulator (FDSOI) MOSFETs with 0.15-/spl mu/m gate length by low-temperature processing below 500/spl deg/C after the gate oxide formation have good on/off characteristics. Comprehensive design guidelines for Ta-gate MOSFETs in the deep-submicrometer regime is provided by investigating a wide range of performance and reliability constraints on the process temperature and the SOI thickness. In the guideline, the recrystallization of the source/drain region gives inferior limits of the SOI thickness and the process temperature. Thermal reaction between Ta and SiO/sub 2/ films sets a superior limit of the process temperature, and a short-channel effect sets a superior limit of the SOI thickness.

Residual‐Surfactant‐Free Photoresist Development Process

The addition of small amounts of surfactant and hydrogen peroxide (H 2 O 2 ) to the developer is shown to improve the performance of the photoresist development process. Exposed photoresist areas are dissolved more uniformly, the smoothness of Si surface is maintained, and carbon contamination during the development process is prevented. Ozone (O 3 ) treated ultrapure water rinsing at room temperature is an efficient way to remove the surfactant adsorbed on Si surface. A surfactant-added developer improves wettability on the photoresist surface, which leads to more uniform developing. The dissolution rate in the exposed photoresist is promoted and the etching rate of Si substrate is suppressed due to the effect of the additional surfactant

Threshold voltage adjustment in SOI MOSFETs by employing tantalum for gate material

The threshold voltages of n-channel and p-channel thin-film Si-on-Insulator (SOI) MOSFETs have been controlled by employing Tantalum (Ta) for gate materials in 1 V applications. The threshold voltage control in SOI MOSFETs by the work function of gate material, that is, work function engineering is needed. In order to suppress the reaction between Ta and gate oxide, low-temperature processing after the gate oxide step was successfully established.

High-performance metal-gate SOI CMOS fabricated by ultraclean low-temperature process technologies

The threshold voltages of thin-film fully-depleted Si-on- insulator (FDSOI) nMOS and pMOS have been controlled by employing tantalum (Ta), one of the high-refractory metals, for the gate material. For the low-power application in deep quarter-micron regime, when the supply voltage becomes around 1.0 V, it is necessary that the threshold voltages of SOI MOSFETs, are controlled by the work function of the gate material: Work Function Engineering. It is clear that the mid-gap material instead of the poly-crystalline silicon (poly-Si) for the gate material is effective to control the threshold voltage. The use of the mid-gap material leads to the simplicity for CMOS processes because the same gate material is available for both nMOS and pMOS. Ta, one of the mid-gap material, has low resistivity and excellent durability to wet chemical cleaning. The ultraclean, low- temperature process makes it possible to suppress the reaction between Ta and the gate oxide. The results have shown that Ta-gate FDSOI MOSFET exhibits excellent threshold voltage adjustment in 1.0 V application, even if the gate length is reduced to 0.15 micrometers .

Enhancement of resolution and linearity control of contact-hole resist patterns with surface-active developer

The resolution enhancement of contact-hole resist patterns featuring precise linear correlation between mask size and resist-pattern size by employing a surface-active developer is presented. The addition of surfactant improves the wettability of the developer, thus enabling the solution to penetrate narrow spaces. The optimum surfactant concentration in developer leads to superior resist performance. This technology for contact-hole patterning results in high resolution, high sensitivity, and a wide process margin for ULSI manufacturing. >

High-sensitivity and high-resolution contact hole patterning by enhanced-wettability developer

We have determined that high-sensitivity and high-resolution contact hole photoresist patterning can be achieved using an optimized combination of developer, added surfactant and ammonium chloride salt. The addition of surfactant improves the wettability of the developer to promote resist dissolution. The presence of ammonium chloride salt protects the sidewall of the contact hole resist pattern to achieve good pattern profile. The optimal developer can form contact hole patterns smaller than the illumination wavelength of the stepper without the use of phase shifting technology.

High-accuracy resist development process with wide margins by quick removal of reaction products

We have demonstrated that highly reliable resist patterning is achieved by effectively removing reaction products by means of ultrasonic development and the addition of surfactant to the developer. It has been found that the reaction products form a stagnant layer, resulting in preventing the resist-developer reaction. Thus, the existence of the stagnant layer leads to the fluctuation of the developing characteristics and the degradation of the resist contrast, resist sensitivity, and process margins. To quickly remove the stagnant layer from the resist-developer reaction interface, two techniques are employed: physical method of developing with ultrasonic agitation and chemical method of the addition of surfactant to developer. In addition, it has been found that the agitation of developer lowers the etch rate of (100) Si and prevents the appearance of pyramid-shaped etch pits on Si surface.

Advanced development process for ultrafine photoresist patterns

Addition of appropriate surfactant to developer will improve wettability of the developer, thus promoting uniformity of dissolution of exposed photoresist. Surface smoothness of the Si substrate is also improved when developer contains surfactant. The only disadvantage is that surfactant is adsorbed onto the wafer surface; however, it can be removed by a Pt-H/sub 2/O/sub 2/ treatment without degrading the photoresist pattern. The optimal tetramethylammonium hydroxide (TMAH) concentration in the developer was investigated by measuring the developing selectivity of the photoresist against various TMAH concentration levels. The developing selectivity is considered to directly affect the photoresist profile and resolution in the development process. >