Takuro Tamura

Switching property of atomic switch controlled by solid electrochemical reaction

We measured the switching time of an atomic switch that is operated by controlling the formation and annihilation of an atomic bridge in a nanogap between two electrodes using solid electrochemical reaction. The switching time becomes exponentially shorter with increasing the switching bias voltage. This exponential relation indicates that the switching time is determined by the solid electrochemical reaction, which is supported by theoretical estimation using a simple model. These results suggest the possibility that the atomic switch can be operated as fast as semiconductor devices currently used.

Material dependence of switching speed of atomic switches made from silver sulfide and from copper sulfide

We developed an atomic switch consisting of an ionic and electronic mixed conductor electrode and a counter metal electrode, having a space of about 1 nm between them. Formation and annihilation of a conductive atomic bridge is controlled using a solid electrochemical reaction, which is caused by applying a certain bias voltage between the electrodes. In this study, we measured the switching time of atomic switches made of silver sulfide and copper sulfide. The switching times were different, and this difference can be attributed to the different activation energies and chemical potentials of the materials.

Prototype of Phase-Change Channel Transistor for Both Nonvolatile Memory and Current Control

We prototyped phase-change (PC) channel transistors and demonstrated two functions of nonvolatile memory and channel current control. We have developed prototype transistors that use a PC channel instead of a silicon channel. The PC material of a Ge2Sb2Te5 thin film with a thickness of 50 nm was used. We demonstrated a memory function whereby we achieved a reversible change between the crystalline and amorphous phases by applying a source-drain (SD) voltage for Joule heating. In the experiment, the applied voltages for PC between amorphous and crystalline phases were from 5 to 8 V. Control of the channel current was realized by applying a gate bias. The SD current was suppressed to less than 1/20 of that at a gate bias of -3 V by applying a gate bias of 0-3 V

Fabrication of 10-nm-Order Block Copolymer Self-Assembled Nanodots for High-Density Magnetic Recording

In this work, we investigated the fabrication of 10-nm-order block copolymer self-assembled nanodots using high-etching-selectivity polystyrene–poly(dimethylsiloxane) (PS–PDMS) block copolymers for high-density storage devices. We adopted PS–PDMS polymers with two different molecular weights of 13,500–4,000 and 11,700–2,900. With decreasing molecular weight, the nanodot size decreased from 12 to 10 nm, and the pitch correspondingly decreased from 22 to 20 nm. The PS–PDMS film thickness is the critical-factor to determine whether nanodot arrays can form on a large area or not. It was demonstrated that the thicknesses of 36 and 33 nm were optimal for the PS–PDMS polymers of 13,500–4,000 and 11,700–2,900, respectively. The limitation in the selection of PS–PDMS to form a smaller size of self-assembled nanodots is also predicted. This work promises to open way toward 1.6 Tbit/in.2 storage device with cheap cost production.

Orientation-Controlled and Long-Range-Ordered Self-Assembled Nanodot Array for Ultrahigh-Density Bit-Patterned Media

In this study, we investigated the control of the orientation and ordering of self-assembled nanodots from a block copolymer (BCP) with the help of a guide pattern created by electron beam (EB) drawing. The guide pattern consisted of a post lattice and guide lines. The former is used to enable self-assembled nanodots from the BCP to be regularly arranged, while the latter is used to control the orientation of the nanodot arrays. It was demonstrated that the combined guide pattern was effective for controlling the BCP dot array to achieve long-range ordering and controlled orientation.

Estimation of Nanometer-Sized EB Patterning Using Energy Deposition Distribution in Monte Carlo Simulation

We have studied on theoretical electron energy deposition in thin resist layer on Si substrate for electron beam lithography. We made Monte Carlo simulation to calculate the energy distribution and to consider formation of nanometer sized pattern regarding electron energy, resist thickness and resist type. The energy distribution in 100 nm-thick resist on Si substrate were calculated for small pattern. The calculations show that 4 nm-wide pattern will be formed when resist thickness is less than 30 nm. Furthermore, a negative resist is more suitable than positive resist by the estimation of a shape of the energy distribution.

Formation of 12-nm Nanodot Pattern by Block Copolymer Self-Assembly Technique

In this work, we studied the fabrication of 12-nm-size nanodot pattern by self-assembly technique using high-etching-selectivity poly (styrene)-poly (dimethyl-siloxane) (PS-PDMS) block copolymers. The necessary etching duration for removing the very thin top PDMS layer is unexpectedly longer when the used molecular weight of PS-PDMS is 13.5-4.0 kg/mol (17.5 kg/mol total molecular weight) than that of 30.0-7.5 kg/mol (37.5 kg/mol total molecular weight). From this experimental result, it was clear that PS-PDMS with lower molecular weight forms thicker PDMS layer on the air/polymer interface of PS-PDMS film after microphase separation process. The 22-nm pitch of nanodot pattern by self-assembly holds the promise for the low-cost and high-throughput fabrication of 1.3 Tbit/inch2 storage device. Nanodot size of 12 nm also further enhances the quantum-dot effect in quantum-dot solar cell.

Fabrication of Nanometer Sized Si Dot Arrays Using Ar Ion Milling with Calixarene Resist Dot Arrays

In this study, we investigated the possibility of forming the fine Si dot arrays by means of electron beam (EB) lithography and dry etching technique for the future’s devices with nano-scale structures. We examined the properties of Ar ion milling for the fabrication of nanometer sized Si dot arrays on a Si substrate. We have succeeded in forming 40 nm pitched Si dot arrays with a diameter of <20 nm using dot array patterns of the calixarene resist as a mask. We also obtained the Ar ion milling property that there exists the horizontal milling rate as well as the vertical milling rate. We formed Si dot arrays with a dot diameter of about 10 nm using this property. It was clarified that Ar ion milling and EB lithography with calixarene resist has the potential to form Si nano dot arrays for the nano devices.

Guide Pattern Functionalization for Regularly Arranged PS-PDMS Self-Assembled Nanodot Pattern by Brush Treatment

We have studied functionalization of guide pattern with brush treatment. Especially, the effect of brush treatment on ordering of nanodots formed on the guide pattern was investigated. We used polydimethylsiloxane (PDMS) as brush modification to form self-assembled nanodots on the guide pattern using polystyrene (PS) - PDMS as block copolymer. The brush treatment using toluene solvent made guide patterns of the electron beam (EB) drawn resist behave like PDMS guide patterns and good ordering of the nanodots has been achieved. It was demonstrated that the brush treatment enabled the PDMS nanodots to be regularly located in the desired positions defined by the EB drawn guide patterns.