Tamotsu Yamashita

Relation between Defects on 4H-SiC Epitaxial Surface and Gate Oxide Reliability

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.

Contrast analysis of Shockley partial dislocations in 4H-SiC observed by synchrotron Berg–Barrett X-ray topography

Shockley partial dislocations in 4H-SiC were observed using monochromatic synchrotron X-ray topography with a grazing-incidence Bragg-case geometry, that is, Berg–Barrett topography. The contrast of partial dislocations at the edges of Shockley-type stacking faults is discussed in terms of whether they have C- or Si-core edge components, or screw components. The dissociated state of basal-plane dislocation is discussed on a basis of the stacking sequence for basal-planes in the 4H-SiC crystal structure. It is expected that the results obtained in this study will be useful for characterizing Shockley-type stacking faults in Berg–Barrett topography.

Reliability of Gate Oxides on 4H-SiC Epitaxial Surface Planarized by CMP Treatment

This work reports about effect of SiC epitaxial-wafer surface planarization by chemo-mechanical polishing (CMP) treatment on electrical properties of SiC-MOS capacitor. We have observed the surface morphology of 4H-SiC epitaxial layer planarized by CMP treatment using a confocal differential interference microscope, and evaluated the reliability of gate oxides on this surface using constant current time-dependent dielectric breakdown (CC-TDDB) and current-voltage (I-V) characteristics. Surface roughness such as step bunching deteriorates drastically the reliability of gate oxide, while the epitaxial-surface planarization by CMP treatment improved oxide reliability due to the high uniformity of the oxide film thickness.

Origin Analyses of Obtuse Triangular Defects in 4deg.-Off 4H-SiC Epitaxial Wafers by Electron Microscopy and by Synchrotron X-Ray Topography

Triangular shaped defects with obtuse-angles at tops and long bases are often observed in surfaces of epitaxial films. We have investigated the origins of them, and it became clear that these defects without clear origins were formed by contaminations of tantalum carbide particles. Formations of micro-order pipes at the origin points of these defects were also observed. These micro-order pipes did not accompany strain and dislocations around them, though their appearances were very similar to the ones so-called micro-pipes.

Origin Analyses of Trapezoid-Shape Defects in 4-Deg.-off 4H-SiC Epitaxial Wafers by Synchrotron X-Ray Topography

The trapezoid-shape defects are one of the most common surface defects on current 4H-SiC epitaxial film surface since they give rise negative impact for MOS-devices. We have investigated structures and origins of the defects. It is discovered that the possible origins of the trapezoid-shape defects are basal plane dislocations (BPDs), threading edge dislocations (TEDs), threading screw dislocations (TSDs),and the short dislocation loops introduced under scratches.

Microstructural Analysis of Damaged Layer Introduced during Chemo-Mechanical Polishing

Damaged layers, which are introduced during chemo-mechanical polishing (CMP) underneath the 4°off-cut 4H-SiC wafer surface and cause surface defects formations after epitaxial films growth, are investigated by scanning electron microscopy (SEM) and transmission electron microscopy (TEM). SEM observations show presence of small scratches on wafer surfaces after CMP process. The widths of such scratches are submicron meters, thus it is hard to detect them by optical microscopy. TEM observations show that high-density regions of dislocation loops exist below scratches and the widths of such dislocation loops are much wider than the morphological width. Details of the dislocation structure are also analyzed. It is shown that the high-density dislocation loops cause local surface roughening on the surface of the epitaxial film.

Characterization of scraper-shaped defects on 4H-SiC epitaxial film surfaces

We have found undiscovered defects on a 4H-SiC epitaxial layer, the shape of which resembles a scraper in images taken by confocal differential interference contrast optical microscopy. The surface morphological structure and formation mechanism of the scraper-shaped defects were investigated by atomic force microscopy and grazing incidence monochromatic synchrotron X-ray topography, respectively. The scraper-shaped defects were surface morphological defects consisting of surface asperity and were caused by the migration of interfacial dislocations. The evaluation of the thermal oxide reliability of metal–oxide–semiconductor capacitors fabricated on these defects was performed by time-dependent dielectric breakdown measurement. The degradation of thermal oxide occurred only on the downstream line of the scraper-shaped defects. The thickness of the oxide layer on these defects was also investigated using cross-sectional transmission electron microscopy.

Characterization of Triangular-Defects in 4° off 4H-SiC Epitaxial Wafers by Synchrotron X-Ray Topography and by Transmission Electron Microscopy

We report our investigation results on triangular-defects formed on 4deg. off 4H-SiC epi- taxial wafers. Triangular-defects that had neither down-falls nor basal-plane dislocations previously reported as origins of triangular-defects at the tips of triangle were investigated by TEM. Our TEM results revealed that foreign materials contamination that were different from well-known down- -falls in size and in composition caused one of the defect formations and abnormal domain forma- tions were implied to occur and thought to relate to defect formations. We also report that several types of microstructure existed in the isosceles of defect during dislocation analyses around triangular-defects by X-ray topography.

Starting Point of Step-Bunching Defects on 4H-SiC Si-Face Substrates

On 4H-SiC Si-face substrates after H2 etching, the defect with “line” feature parallel to a step as “bunched-step line” was observed. Using X-ray topography and KOH etching, we confirmed that the bunched-step line originated from basal plane dislocation (BPD). Use of the substrate with the lowest BPD density will be effective to reduce bunched-step line that would affect oxide layer reliability on an epitaxial layer. However, more detail investigation needs to classify the BPD that would become a starting point of bunched-step line.

Electrical Characteristics/Reliability Affected by Defects Analyzed by the Integrated Evaluation Platform for SiC Epitaxial Films

The Integrated Evaluation Platform for SiC wafers and epitaxial films is established and provide TDDB reliability data such as Qbd. Accumulated numerous Qbd data derived from the platform shows three discrete universal distributions (D1>D2>D3) mainly affected by step bunching. On the fairly flat surface, locally spreading step-bunching area formation is caused by the scratches on the CMP surface. The step-bunching area contains large number of step-bunching lines, which correspond to trapezoid-shape defects, stretching in a low along the scratches. Only the downstream bases of the trapezoid-shape defects degrade the Qbd into D2 from D1 on the flat surface without step bunching.