Tang Hualian

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

A power-efficient 12-bit 40-MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two opamp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode (RFC) amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADCs performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range (SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio (SNDR) of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.43 to +0.48 LSB and −1.62 to +1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure-of-merit (FOM) of 0.63 pJ per conversion-step.

An I/Q DAC with gain matching circuit for a wireless transmitter

This paper presents a two-channel 12-bit current-steering digital-to-analog converter (DAC) for I and Q signal paths in a wireless transmitter. The proposed DAC has a full-scale output current with an adjusting range of 2 to 10 mA. A gain matching circuit is proposed to reduce gain mismatch between the I and Q channels. The tuning range is ±24% of full scale and the minimum resolution is 1/16 LSB. To further improve its dynamic performance, the switch driver and current cell are optimized to minimize glitch energy. The chip has been processed in a standard 0.13 μm CMOS technology. Gain mismatch between a I-channel DAC and a Q-channel DAC is measured to be approximately 0.13%. At 120-MSPS sample rate for 1 MHz sinusoidal signal, the spurious free dynamic range (SFDR) is 75 dB. The total power dissipation is 62 mW and has an active area of 1.08 mm2.