Tang-Nian Luo

A 0.8-mW 55-GHz Dual-Injection-Locked CMOS Frequency Divider

This paper presents the dual-injection-locking technique to enhance the locking range of resonator-based frequency dividers. By fully utilizing the voltage and current injection of the input signal, the divider locking range is extended significantly. The 0.8-mW dual-injection-locked frequency divider was developed in 90-nm digital CMOS technology. The total chip size is 0.77 mm times 0.5 mm. Without any varactor or inductor tuning, the input signal frequency coverage of the divider is from 35.7 to 54.9 GHz. Combined with the excellent locking range and sub-milliwatt power consumption, the figure-of-merit of this work surpasses those of the previous resonator-based dividers by more than one order.

A 60-GHz 0.13-

This paper presents the design and analysis of a 60-GHz 0.13-mum CMOS divide-by-three frequency divider (FD). The regenerative injection-locked technique is proposed to achieve divide-by-three function at millimeter-wave frequency. The novel level shifter is used to increase the overdrive voltage of the input switch of the loop divider such that the divider locking range and input sensitivity can be enhanced. The CMOS divide-by-three FD including the testing pads occupies the silicon area of 0.99 mm × 0.69 mm. Operated at 1.3 V, the CMOS divider consumes 13 mW of power. The measured locking range is 1.8 GHz around the input frequency of 59 GHz, and the phase noise of the output signal at 1-MHz offset is -131.36 dBc/Hz.

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This paper presents a 77-GHz CMOS frequency-modulated continuous-wave (FMCW) frequency synthesizer with the capability of reconfigurable chirps. The frequency-sweep range and sweep time of the chirp signals can be reconfigured every cycle such that the frequency-hopping random chirp signal can be realized for an FMCW radar transceiver. The frequency synthesizer adopts the fractional-N phase-locked-loop technique and is fully integrated in TSMC 65-nm digital CMOS technology. The silicon area of the synthesizer is 0.65 mm × 0.45 mm and it consumes 51.3 mW of power. The measured output phase noise of the synthesizer is -85.1 dBc/Hz at 1-MHz offset and the root-mean-square modulation frequency error is smaller than 73 kHz.

CMOS Divide-by-Three Frequency Divider

This letter presents a V-band wide-locking range divide-by-four frequency divider implemented in 90-nm digital CMOS technology. A sub-harmonic mixer (SHM) is adopted in the regenerative divider architecture to realize the division ratio of four. The splitting supply and parallel inductive peaking techniques are applied to the mixer design to boost the conversion gain, which is the bottleneck of the dividers locking range. Operated at 1.2 V, the frequency divider consumes 15.5 mW of power and generates four-phase output signals. The measured locking range is 5.4 GHz with the input signal power smaller than 0 dBm.

A 77-GHz CMOS FMCW Frequency Synthesizer With Reconfigurable Chirps

An integrated 1-V, 50-GHz CMOS voltage-controlled-oscillator (VCO) is presented for the emerging 60-GHz UWB applications. Implemented in a commercial 0.18/spl mu/m CMOS technology, the core VCO circuitry consumes 4mW of power and occupies only 90/spl mu/m/spl times/120/spl mu/m of the silicon estate. The high quality-factor line inductors and NMOS varactors are used to construct the LC-resonators. The measured phase noise at 1-MHz offset from 49 GHz is -96 dBc/Hz, which leads to an excellent figure-of-merit (FOM) of -184 dBc/Hz.

A V-Band Divide-by-Four Frequency Divider With Wide Locking Range and Quadrature Outputs

A 2.4-GHz Doherty power amplifier (PA) is developed in 0.18-mum CMOS technology. An automatic adaptive bias control circuit is integrated with the auxiliary PA to improve the overall performance of the PA. Operated at 3V, the P1 dB and associated power-added-efficiency (PAE) of the PA are 21dBm and 33%, respectively. At the output power 6-dB backoff from P1 dB, the PAE remains 21%. The limited PAE degradation at backoff power levels makes the PA suitable for the applications with high peak-to-average power ratio

A 1-V CMOS VCO for 60-GHz applications

This paper presents a novel low-voltage low-phase-noise LC quadrature voltage controlled oscillator (QVCO) implemented in the TSMC 0.18-μm CMOS process. By using a combination of bottom-series coupling architecture and capacitor tapping technique, the QVCO achieves a zero resonator phase shift (RPS), a high loaded resonator quality factor, and limited phase noise contribution from the current source, all of which lead to a low phase noise. From a 5.3-GHz carrier, the measured phase noise is −123 dBc/Hz at 1-MHz offset with a 1.8-V power supply and −118 dBc/Hz at 1-MHz offset with a 1-V power supply.

A High-Efficient CMOS RF Power Amplifier With Automatic Adaptive Bias Control

This letter presents a millimeter-wave 90 nm CMOS divide-by-four frequency divider using self-mixing technique. The output of the push-push oscillator mixes with the input signal, and the resulting intermediate frequency signal locks the fundamental oscillation frequency of the oscillator at exactly one-fourth of the input signal frequency. The frequency divider is implemented in TSMC 90 nm 1P9M digital CMOS technology and the overall die size is 0.91 mm times 0.53 mm. For low-power mode, the divider consumes only 0.8 mW with a 0.8 V supply voltage, and the measured locking range is 300 MHz. For normal mode, the divider consumes 2 mW with a 1 V supply, and the locking range is extended to 1100 MHz. The operating range of the divider covers from 46.1 to 52.8 GHz with varactor tuning and band switching.

A low-voltage low-phase-noise bottom-series LC QVCO using capacitor tapping technique

This paper presents a V-band wide locking range 0.18-μm CMOS frequency divider. The resonator-based injection-locked frequency dividers (ILFD) inherently suffer from narrow locking range. The combination of common-node injection and direct injection is proposed to improve the signal injection efficiency and locking range. Compared to the conventional direct injection technique, the proposed technique is capable of doubling the divider’s locking range. Operated at 1.4 V, the frequency divider core consumes 2.8 mW of power. The measured free running frequency and output power of the divider are 28.17 GHz and −22.84 dBm, respectively. The locking range is 4.9 GHz around the input frequency of 56 GHz. With high operating frequency, wide locking range, and low power consumption, this work achieves the excellent figure-of-merit (FOM), which is much better than the frequency dividers implemented in the same generation CMOS process. The overall chip size is 0.77 × 0.49 mm2.

A Millimeter-Wave 90-nm CMOS Self-Mixing Frequency Divider

This paper presents a wide operation range 0.18mum CMOS frequency divider for 60GHz wireless applications. The direct injection lock technique is used to perform the signal division at millimeter-wave frequency. The deep n-well is implemented under the NMOS switch transistor to improve the lock range of the frequency divider. Combined with band switching and analog frequency tuning, the operation range of the frequency divider covers from 43 to 49 GHz. Operated at 1V, the frequency divider consumes 8mW of power. The core circuit of the frequency divider occupies 200mum times 320mum of silicon estate