Yi-Jan Emery Chen

A 0.8-mW 55-GHz Dual-Injection-Locked CMOS Frequency Divider

This paper presents the dual-injection-locking technique to enhance the locking range of resonator-based frequency dividers. By fully utilizing the voltage and current injection of the input signal, the divider locking range is extended significantly. The 0.8-mW dual-injection-locked frequency divider was developed in 90-nm digital CMOS technology. The total chip size is 0.77 mm times 0.5 mm. Without any varactor or inductor tuning, the input signal frequency coverage of the divider is from 35.7 to 54.9 GHz. Combined with the excellent locking range and sub-milliwatt power consumption, the figure-of-merit of this work surpasses those of the previous resonator-based dividers by more than one order.

A Compact Wideband CMOS Low Noise Amplifier With Gain Flatness Enhancement

This paper presents a compact 0.18-¿m CMOS wideband gain-flattened low noise amplifier (LNA). The low noise characteristic of the LNA is achieved by the noise canceling technique and the gain flatness is enhanced by the gate-inductive gain-peaking technique. In addition to extending flat-gain bandwidth, the proposed gain-peaking technique results in better wideband noise canceling and quick gain roll-off outside the desired signal band to reject interference. Without using any passive inductor, the core size of the fully-integrated CMOS LNA circuit is only 145 ¿ m × 247 ¿ m. The measured gain and noise figure of the CMOS LNA are 16.4 dB and 2.1 dB, respectively. The gain variation of the LNA is ±0.4 dB from 50 to 900 MHz. Operated at 1.8 V, the chip consumes 14.4 mW of power.A low drop-out (LDO) regulator with a feed-forward ripple cancellation (FFRC) technique is proposed in this paper. The FFRC-LDO achieves a high power-supply rejection (PSR) over a wide frequency range. Complete analysis and design steps of the FFRC-LDO are presented in this paper. Kelvin connection is also used to increase the gain-bandwidth of the LDO allowing for faster transient performance. The LDO is implemented in 0.13 ¿m CMOS technology and achieves a PSR better than - 56 dB up to 10 MHz for load currents up to 25 mA. Load regulation of 1.2 mV for a 25 mA step is measured, and the whole LDO consumes a quiescent current of 50 ¿A with a bandgap reference circuit included. To our knowledge, this is the first LDO that achieves such a high PSR up to 10 MHz.

A Miniaturized 3 dB Branch-Line Hybrid Coupler With Harmonics Suppression

This letter presents a miniaturized 3 dB branch-line hybrid coupler with second harmonic suppression using high-impedance transmission lines and interdigitated shunt capacitors. By using the interdigitated capacitors shunt with the transmission lines, further minimization of the 3 dB branch-line hybrid coupler can be achieved compared with previously reported techniques. The design of the interdigitated shunt capacitors requires concurrent optimization of the capacitance to the ground and the edge-coupling interdigitated capacitance between the ports. For validation, a miniaturized 3 dB branch-line hybrid coupler at 836.5 MHz was designed and implemented. The proposed 3 dB branch-line hybrid coupler achieved a compact size of 27.75 mm × 25.7 mm, or equivalently 0.077λo×0.072λo, where λo is the free-space wavelength. Moreover, the coupler can suppress second harmonic components by 20 dB while maintaining similar measured performance compared to the conventional branch-line hybrid coupler.

A 0.6-V Low Power UWB CMOS LNA

This paper presents the design of a low-power ultra-wideband low noise amplifier in 0.18-mum CMOS technology. The inductive degeneration is applied to the conventional distributed amplifier design to reduce the broadband noise figure under low power operation condition. A common-source amplifier is cascaded to the distributed amplifier to improve the gain at high frequency and extend the bandwidth. Operated at 0.6V, the integrated UWB CMOS LNA consumes 7mW. The measured gain of the LNA is 10dB with the bandwidth from 2.7 to 9.1GHz. The input and output return loss is more than 10dB. The noise figure of the LNA varies from 3.8 to 6.9dB, with the average noise figure of 4.65dB. The low power consumption of this work leads to the excellent figure of gain-bandwidth product (GBP) per milliwatt

A 60-GHz 0.13-

This paper presents the design and analysis of a 60-GHz 0.13-mum CMOS divide-by-three frequency divider (FD). The regenerative injection-locked technique is proposed to achieve divide-by-three function at millimeter-wave frequency. The novel level shifter is used to increase the overdrive voltage of the input switch of the loop divider such that the divider locking range and input sensitivity can be enhanced. The CMOS divide-by-three FD including the testing pads occupies the silicon area of 0.99 mm × 0.69 mm. Operated at 1.3 V, the CMOS divider consumes 13 mW of power. The measured locking range is 1.8 GHz around the input frequency of 59 GHz, and the phase noise of the output signal at 1-MHz offset is -131.36 dBc/Hz.

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This paper presents a systematic design methodology for broad-band CMOS low-noise amplifiers (LNAs). The feedback technique is proposed to attain a better design tradeoff between gain and noise. The network synthesis is adopted for the implementation of broad-band matching networks. The sloped interstage matching is used for gain compensation. A fully integrated ultra-wide-band 0.18-mum CMOS LNA is developed following the design methodology. The measured noise figure is lower than 3.8 dB from 3 to 7.5 GHz, resulting in the excellent average noise figure of 3.48 dB. Operated on a 1.8-V supply, the LNA delivers 19.1-dB power gain and dissipates 32 mW of power. The gain-bandwidth product of the UWB LNA reaches 358 GHz, the record number for the 0.18-m CMOS broad-band amplifiers. The total chip size of the CMOS UWB LNA is 1.37 times 1.19 mm2.

CMOS Divide-by-Three Frequency Divider

This paper explores different levels of integration for CMOS RF power amplifiers, including integration fully on chip, integration with LTCC passive components, and integration with off-chip components. At 1.9 GHz, the fully on-chip integrated CMOS PA can deliver 20 dBm output power with 16% efficiency. Because the LTCC inductors have much higher Q than the on-chip inductors, the CMOS PA integrated with passive components embedded in LTCC can improve the output power and efficiency to 24 dBm and 32% at 1.9 GHz, respectively. The 2.4 GHz Bluetooth PA with discrete passive components for output matching exhibits 22 dBm output power and 44% efficiency. To our knowledge, this paper reports the first development of fully on-chip integrated and LTCC hybrid CMOS power amplifiers.

Development of Integrated Broad-Band CMOS Low-Noise Amplifiers

We present a comprehensive investigation of the cryogenic performance of third-generation silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology. Measurements of the current-voltage (dc), small-signal ac, and broad-band noise characteristics of a 200-GHz SiGe HBT were made at 85 K, 120 K, 150 K, 200 K, and 300 K. These devices show excellent behavior down to 85 K, maintaining reasonable dc ideality, with a peak current gain of 3800, a peak cut-off frequency (f/sub T/) of 260 GHz, a peak f/sub max/ of 310 GHz, and a minimum noise figure (NF/sub min/) of approximately 0.30 dB at a frequency of 14 GHz, in all cases representing significant improvements over their corresponding values at 300 K. These results demonstrate that aggressively scaled SiGe HBTs are inherently well suited for cryogenic electronics applications requiring extreme levels of transistor performance.

RF power amplifier integration in CMOS technology

This paper presents a transmitter architecture based on a pulse-modulated polar transmitter using multiphase pulsewidth modulation. The modulation to the radio-frequency input signal, instead of conventional drain modulation, significantly reduces the circuit complexity, while the multiphase modulation technique reduces the out-of-band emissions. An 836.5-MHz four-phase prototype transmitter using four class-C power amplifiers in parallel was constructed. Using the transmitter, single-phase, two-phase, and four-phase pulsewidth modulated signals were tested to verify the benefits of using the proposed multiphase architecture. Using a CDMA2000 1X signal, 46.8% efficiency at a 29-dBm output power level was measured while passing the spectral-mask requirements without using any kind of digital predistortion or calibration.

Cryogenic operation of third-generation, 200-GHz peak-f/sub T/, silicon-germanium heterojunction bipolar transistors

This paper presents the development of the wideband power amplifier (PA) for application to intelligent cognitive radios. The load-tracking based on the frequency-varied load-pull technique is proposed for the PA design. The load impedance tracking is realized by filter network synthesis. A 3-7.5-GHz broadband PA is demonstrated in 0.15-mum InGaAs pseudomorphic HEMT technology. Operated at 3.5 V, the P1 dB and power-added efficiency of the PA are better than 21.4 dBm and 20%, respectively.