Tanya Nigam

Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies

Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing procedure is introduced. This utilizes the PCI card characterization methodology to highlight a close link between BTI variability and RDF, and to discuss the impact of BTI recovery and wafer-to-wafer variation on the BTI statistics. We demonstrate a correlation between time-zero VT and ΔVT and illustrate the minor impact of BTI induced variability on post-stress VT distributions relevant for modeling the circuit aging.

Impact of charge trapping on the voltage acceleration of TDDB in metal gate/high-k n-channel MOSFETs

The root cause for the increase in the TDDB voltage acceleration with decreasing stress voltage in metal gate/high-k n-channel FETs is investigated. Using DC and AC stress methodologies, the effect could be linked to charge trapping in the high-k gate dielectric. Furthermore, a correction for charge trapping is proposed, which results in a single power law voltage dependence for all stress conditions.

Impact of Transistor Level degradation on product reliability

Product level lifetime margins, determined by HCI and BTI, are shrinking with scaling. Accurate device-level HCI degradation models, together with known BTI models, are needed to predict frequency degradation of a ring oscillator. Both NBTI and HCI exhibit relief during AC operation and the respective contribution to RO frequency degradation is a function of applied bias.

Correlation of BTI induced device parameter degradation and variation in scaled Metal Gate / High-k CMOS technologies

The correlation between time-zero device parameter and BTI induced parameter degradation is studied in detail. The device overdrive remains the dominant factor in the ΔI_dsat for ultra-narrow logic gates while ΔV_Tlin shows a weak but measurable correlation to the time-zero value. The correlation has an impact on the σ-values of V_Tlin for stressed devices and should be considered for more accurate circuit aging simulations.

Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process

We compare the intrinsic reliability of the dielectric stack of a high performance bulk planar 20nm replacement gate technology to the reliability of high performance bulk planar 28 nm gate first high-k metal gate (HKMG) technology, developed within the IBM Alliance. Comparable N/PFET TDDB and comparable/improved NFET PBTI are shown to be achievable for similar Tinv. The choice to not include channel silicon germanium as a PFET performance element in the 20nm technology impact NBTI, driving a potential tradeoff between NBTI and PBTI. The complexity of integrating such performance elements while accounting for reliability/performance tradeoffs demands their selection during technology definition with due consideration to realistic product usage conditions.

Fast Wafer-Level Stress-and-Sense Methodology for Characterization of Ring-Oscillator Degradation in Advanced CMOS Technologies

Ring oscillators (ROs) are widely used to study the degradation of logic CMOS circuits. To successfully link the time dependence of the ROs frequency degradation to the degradation of discrete device, we introduce a novel, fast wafer-level stress-and-sense methodology. With this new methodology, we unambiguously show the close correlation between discrete device degradation and circuit aging at typical wafer-level stress times.

Reliability-performance trade-off for work-function optimization in advanced node replacement metal gate technology

In this work, we explore the complex interaction of the gate stack process and time-dependent-dielectric breakdown (TDDB) in high-K (HK) replacement metal gate (RMG) n-metal-oxide-semiconductor field effect transistors (nMOSFETs). TDDB is a key reliability metric governing the product lifetimes under long-term operation. Based on this study, it is observed that TDDB is greatly modulated by the proximity of Al to the MG/HK interface. The key parameter modulated by gate stack optimization is voltage acceleration exponent (VAE) for TDDB. All observations indicate higher VAEs can be achieved by keeping the Al away from the MG/HK interface.

Scaling to the final frontier: Reliability challenges in sub 20 nm technologies

Summary form only given. At the Industrial Surveillance Day, ASFINAG and the Alpen Adria Universitt Klagenfurt (in particular the Institute of Information Technology and the Institute of Networked and Embedded Systems) demonstrate a show case of their video-based level of service (LOS) classification for smart cameras. This LOS classification system has been developed in a joint Lakeside Labs project in Klagenfurt, Austria. It is part of a case study which aims at improving the quality of traffic messages for the two particular traffic situations level-of-service (LOS) and weather-related road conditions (WRRC) on two dedicated test tracks on Austrian motorways. Using a live connection to a smart camera at one of these test tracks, we plan to show a live demonstration for visual speed estimation and LOS classification. This demo is coordinated with our partner SLR Engineering, which provided the smart cameras for the case study.

Device reliability metric for end-of-life performance optimization based on circuit level assessment

Performance enhancement is critical for offering competitive CMOS solutions for advanced technology nodes. To fully leverage performance enhancement elements the device reliability impact needs to be comprehended on the CMOS circuits like SRAM and ring-oscillators. We reaffirm that time-zero and BTI induced stochastic variation are most critical for SRAM circuits while for logic circuits such as ring-oscillators the focus is on the mean degradation. In addition we explore the impact of self-heating on the correlation of device to circuit degradation for the FinFET device architecture.

Impact of e-SiGe S/D processes on FinFET PFET TDDB reliability

The impact of source/drain e-SiGe process engineering on time dependent dielectric breakdown (TDDB) on core PFETs fabricated with bulk FinFET technology is evaluated. It is observed that thicker e-SiGe buffer layer improves the PFETs TDDB. Electrical and physical analysis revealed that with thinner buffer layer, Ge atoms migrate to gate dielectric and accelerate the breakdown mechanisms due to poor surface roughness and stoichiometry. In addition, the process optimization of pre-baking of e-SiGe trench can also improve the TDDB even for relatively thinner buffer layer.