Taotao Yan

A low flicker noise and high IIP2 downconversion mixer for Zero-IF GSM receiver

This paper proposes the design of a low flicker noise and high input-referred IP2 (IIP2) down-conversion mixer for Zero-IF GSM receiver in 0.18um CMOS process. The current driven passive mixer topology is adopted due to its low flicker noise and high linearity instincts. Simulation results show that this mixer achieves a conversion gain of 23.1dB with 940MHz local oscillator input signal, a flicker noise corner frequency of 2.5KHz and out of band IIP2 above 70dBm at the total current of 17mA.

A digitally calibrated CMOS RMS power detector for RF automatic gain control

This paper presents the design and implementation of a digitally calibrated CMOS wideband radio frequency (RF) root-mean-square (RMS) power detector for high accuracy RF automatic gain control (AGC). The proposed RMS power detector demonstrates accurate power detection in the presence of process, supply voltage, and temperature (PVT) variations by employing a digital calibration scheme. It also consumes low power and occupies a small chip area. The measurement results show that the scheme improves the accuracy of the detector to better than 0.3 dB over the PVT variations and wide operating frequency range from 0.2 to 0.8 GHz. Implemented in a 0.18 μm CMOS process and occupying a small die area of 263 × 214 μm2, the proposed digitally calibrated CMOS RMS power detector only consumes 1.6 mA in power detection mode and 2.1 mA in digital calibration mode from a 1.8 V supply voltage.

A highly linear wideband variable gain CMOS balun-LNA

This paper presents a highly linear wideband variable gain CMOS Low Noise Amplifier (LNA) that supports single-ended input while providing differential output. The impacts of biasing and parasitic capacitance on gain, noise and linearity are investigated and a new gain tuning method is proposed. The proposed wideband LNA is designed in a 0.18 µm CMOS process. The post-layout simulations show the proposed LNA has a maximum gain of 18 dB and a tunable gain range of 23.1 dB. The LNA shows a noise figure (NF) from 2.16 dB to 2.31 dB at maximum gain mode, a third-order input-referred intercept point (IIP3) of 10.36 dBm and an input referred 1-dB compression point of 1.66 dBm. The return loss S11 is better than −11.0 dB in the frequency range from 470 to 870 MHz. The proposed LNA consumes 5.93 mA from a 1.8 V power supply.

A 0.25dB gain step high linear programmable gain amplifier

A 0.25dB gain step high linear and accurate digitally programmable gain amplifier (PGA) is presented in this paper. The PGA consists of a coarse stage PGA, a fine stage PGA and a buffer. The voltage gain of the coarse PGA can be changed from −6dB to 17dB with 1dB steps and has a −3dB bandwidth of 35MHz. In order to optimize the linearity and gain accuracy, a new structure resistor array is proposed to realize the 0.25dB step fine PGA. The fine PGA shows a dB-linear range of 11.75dB (−5.75dB to 6dB) with a gain error of less than 0.09dB. The proposed PGA circuit is designed in a 0.18um CMOS process and the simulation results show that the PGA has the output-referred third-order interception (OIP3) of 39.7dBm and THD of −79.84dB at −1dBVp-p output voltage, with a current consumption of 2.2mA from a 1.8V supply.

A 1.8V CMOS polar transmitter front-end for 900MHz EDGE system

A 900MHz low-noise high-linearity polar transmitter front-end for EDGE system is presented, including a multiplier as well as a driver amplifier. The whole circuit is implemented in IBM 0.18µm CMOS process. The multiplier and DA provide output power ranging from −30dBm to 4.5dBm, an ACPR of −63dBc at 400KHz offset and an output noise of −167dBm/Hz at 20MHz offset. The spurious around 2^nd and 3^rd harmonics are −46dBc and −39dBc respectively. The carrier suppression is −45dBc. The whole circuit consumes 23∼56mA from a 1.8V supply voltage according to different gain levels.