Tapas Dutta

Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure

We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal–ferroelectric–insulator–semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal–ferroelectric–metal–insulator–semiconductor structure.

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau-Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.

Quantum Confinement Effects in Extremely Thin Body Germanium n-MOSFETs

We explore the impact of varying channel thickness (from 8 to 1.5 nm) on extremely thin germanium n-MOSFETs, by explicitly incorporating the quantum confinement effects in the band structure calculations using the first principle density functional theory. In Ge (001) thin films in the sub-10-nm regime, the X valley becomes the lowest conduction band valley and is mostly responsible for the charge transport as in silicon. Considering device parameters as per the international technology roadmap for semiconductors (ITRS) projected device specifications for the year 2024, we use the confinement-modulated effective mass to calculate the drain current employing the fully ballistic nonequilibrium Greens function transport model. The best suited thickness for digital applications is found to be 1.5 nm with subthreshold slope of 83.8 mV/decade, ION/IOFF of 1.8 × 104, and an ION exceeding ITRS targets.

Impact of Channel Thickness Variation on Bandstructure and Source-to-Drain Tunneling in Ultra-Thin Body III-V MOSFETs

In nanoscale MOSFETs with sub-10 nm channels, the source-to-drain tunneling is expected to be a critical bottleneck, especially in III-V devices on account of their extremely low effective masses. Also, to maintain electrostatic integrity at extremely small gate lengths, the channels need to be made ultrathin. In such devices, the bandstructure of the channel material becomes thickness dependent due to quantum confinement effects, and deviates remarkably from that of the bulk material. In this paper, we use first principle density functional theory calculations to evaluate the variation of the effective mass and bandgap with channel thickness. Then, we perform semi-classical ballistic and full quantum non-equilibrium Greens function transport simulations to study the impact on source-to-drain tunneling in III-V nMOSFETs. We demonstrate that the severity of the expected degradation due to source-to-drain leakage is reduced significantly, when the beneficial impacts of change in bandstructure, and multi-valley transport are taken into account.

Accurate Boundary Condition for Short-Channel Effect Compact Modeling in MOS Devices

In this paper, the boundary conditions at the edges of the junctions are discussed, and their consequences on the compact modeling of short-channel effects (SCEs) in MOSFETs are investigated. It is first shown that the previous voltage-doping transform (VDT) potential model does not agree with the simulation results when the impact of lightly doped drain regions or thin spacers are considered. A solution is then proposed to correct the channel potential model using more accurate boundary conditions at the edges of the channel, which consist in calculating an accurate effective built-in potential value Vbieff at the source and at the drain. The impact of these improved boundary conditions on compact models of SCEs is investigated. It is shown that the previous VDT models of drain-induced barrier lowering and subthreshold swing for all types of fully depleted devices can be very simply corrected to finely agree with the simulations without fitting parameters. These models finally allow to investigate the impact of the doping concentration of the junctions on the device performance.

Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM

We compare the performance of static random access memory (SRAM) cells based on negative capacitance (NC) FinFETs and reference FinFETs at the 7-nm technology node. We use a physics-based model for NC FinFETswhere we couple the Landau–Khalatnikovmodel of ferroelectric materials with the standard BSIM-CMG model of FinFET. For the reference FinFETs, we use the predictive model parameters optimized for SRAM design as per the ASAP7 PDK. We exploit the unique characteristics of NC-FinFETs and demonstrate that for ferroelectric thickness below a critical value, SRAMs with higher hold and read stability, better write-ability, lower leakage as well as faster read access time can be designed at the cost of increased write delay.