Masakatsu Suda

A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input

An on-chip jitter measurement circuit in 0.18 /spl mu/m CMOS is demonstrated, using a combination of a programmable delay line, interleaving PFD, and programmable charge pumps. The method does not require a reference clock. Interleaving PFD minimizes bias errors. Measurement linearity is 3.5 /spl mu/V/ps with an error of 1.03ps/sub rms/ for a 2GHz clock.

1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications

A high-speed high-precision dynamic arbitrary timing generator, fabricated in a 0.18mum CMOS process, for >4GHz ATE applications is demonstrated. It exhibits a maximum operating frequency of 1.066 and 4.266GHz (multiplexed mode), a timing resolution of 1.83ps, an INL of <plusmn4ps excluding the calibration RAM, and a random jitter of <0.7psrms

CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system

This paper presents solutions to realize a high-speed, high-precision CMOS timing generator for a 4.266-Gbps memory test system. In order to realize such a timing generator, we developed a 1.066-GHz CMOS timing generator circuit using a high-speed digital delay locked loop circuit and a high-speed, low-INL fine delay circuit. Consequently, we realized a timing generator with 1/20 the size, 4/9 the power, and frac12 the timing error (INL = 8 ps, total jitter =16.8 ps) compared with a conventional timing generator fabricated by the same CMOS process

34.1 Gbps low jitter, low BER high-speed parallel CMOS interface for interconnections in high-speed memory test system

To solve the transmission bottleneck inside ATE systems, we developed a high-speed parallel CMOS interface macro, which is flexibly applicable to ASICs in ATE systems. The interface macro is capable of providing up to 16 TX and/or RX channels: Moreover, multiple macros can be implemented to one chip. The interface macro is capable of transmitting from DC to 34.1 Gbps (2.13 Gbps/spl times/16 channels). In order to achieve ultra-low BER, we have developed a low-jitter digital delay locked loop circuit as a 4-phase clock source for SerDes circuits. This solution yields 1.5 ps rms of random jitter. The random jitter of this macro is less than one-eighth of the interface using PLL. The eye-opening reaches 0.7UI at BER=10/sup -19/.

Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing

A dynamic arbitrary jitter injection method that can be integrated into our high speed and high density CMOS timing generator has been developed. This method makes it possible to inject arbitrary jitter including Periodic Jitter, Random Jitter and Data Dependent Jitter in order to realize flexible SerDes device testing. By this method, furthermore, jitter injection is dynamically and synchronously controllable according to a test pattern. We have implemented our jitter injection method in a prototype chip to demonstrate the concept. The chip includes a 6.5Gb/s timing generator and was fabricated by a 90nm CMOS process. Area and power consumption for each edge including the jitter injection scheme and timing generator are 0.2mm2 and 43.8mW respectively.

2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device

A differential time-to-digital converter (TDC), fabricated in 0.18 mum CMOS process, for source-synchronous device testing is demonstrated. It exhibits a maximum sampling rate of 2.133 GS/s, a variable resolution of 10-40 ps, an infinite measurement range, an INL of 8.5 ps(pk-pk), and a jitter of 18.3 ps(pk-pk). It is available to be applied to the jitter histogram measurement without dead-time because it detects all transition timing continuously. Furthermore, a possible application of this TDC to ADC or DAC is suggested.

Multi Strobe Circuit for 2.133GHz Memory Test System

This paper presents solutions to reduce measurement error and test time in an AC characteristic test of a source-synchronous device. In order to realize such a solution, we developed a multi strobe circuit which detects a phase difference between output clock and output data at a test cycle in real time without strobe scanning. We implemented a digital delay locked loop for precise multi strobe circuit. We achieved less than 1/5 the measurement error and less than 1/16 the test time compared with the conventional test method