Marius Orlowski

A statistical polishing pad model for chemical-mechanical polishing

Chemical mechanical polishing (CMP) has emerged as a critical technology for advanced integrated circuit fabrication. This paper presents for the first time a physical CMP model that includes the effects of polishing pad roughness and dynamic interaction between pad and wafer. Two new feature-scale polishing mechanisms based on asperity theory are proposed and investigated experimentally. a statistical asperity model is first introduced and applied to characterize surface roughness of polishing pads. The data is then used to calculate pad-wafer contact properties and predict feature-scale polishing rates. CMP experiments suggest that the time-dependent deformation of polishing pads and asperity-device interaction both affect planarization of device features.<<ETX>>

Fluorine diffusion on a polysilicon grain boundary network in relation to boron penetration from P/sup +/ gates

The combined effect of boron penetration and fluorine transport from P/sup +/ polycrystalline gates on flat-band voltage is studied. The SIMS concentration depth profiles elucidate the effect of annealing temperature on the fluorine transport, which in turn affects the boron penetration induced change in flat-band voltage. The fluorine diffusion in the poly gate is dominated by grain boundary diffusion. The identification of this mechanism is supported by SIMS profiles and a simulation based on a new methodology of network diffusion.<<ETX>>

Fully-depleted SOI devices with TaSiN gate, HfO 2 gate dielectric, and elevated source/drain extensions

We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.

Parameter correlation and modeling of the power-law relationship in MOSFET hot-carrier degradation

Correlation between the parameters A and n in the empirical hot-carrier degradation formula, parametric shift=A*t/sup n/, is reported for both n- and p-channel MOSFETs fabricated with various submicrometer processing technologies. Analysis of data indicates that A increases with a decreasing value of n, satisfying a simple exponential relationship, A= alpha *exp(- beta n), within the stress conditions considered. A phenomenological model to explain this relation is provided. Implications for device lifetime prediction under different hot-carrier injection stress conditions are also indicated.<<ETX>>

Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions

We report for the first time, the digital and analog performance of sub-100nm Fully-Depleted Silicon-On-Insulator (SOI) n and p-MOSFETs using TaSiN gate and HfO/sub 2/ dielectric with elevated Source/Drain (SD) extensions. As CMOS technology continues to scale down, the FDSOI technology offers a potential solution to control short channel effects by reducing the silicon film thickness and a concurrent scaling of the buried oxide thickness. The use of metal gate and thin undoped body offer the additional advantages of 1) suppression of polysilicon depletion effects, 2) elimination of boron penetration, 3) minimizing S/D junction capacitance (Cj), and 4) enhancing transistor matching performance for mixed signal application. High k dielectric is necessary to reduce gate leakage for EOT below 15 to 20/spl Aring/. The intrinsic low-leakage nature of the FDSOI device and its immunity to floating body effect provides much opportunity for ultra-low power digital and analog applications. Physical and electrical analyses of the devices are presented to provide an assessment of the metal gates on high K gate dielectric in combination with fully-depleted device operation in the context of digital and analog circuits.

Combined asperity contact and fluid flow model for chemical-mechanical polishing

This paper presents, for the first time, a physical model of chemical-mechanical polishing (CMP) that combine the effects of polishing pad roughness and slurry hydrodynamic pressure. Recently, the authors introduced a statistical asperity model to analyze contact of wafer and the polishing pad. This model is extended to include slurry flow hydrodynamics. Fluid film thickness between the wafer and pad is first estimated from measured pad roughness. Fluid pressure is then calculated from finite element simulation. The model is used to investigate parametric effects of pressure, platen velocity and pad roughness.<<ETX>>

The effect of low‐thermal‐budget anneals and furnace ramps on the electrical activation of arsenic

The electrical activation of arsenic under low‐thermal‐budget anneals has been studied by annealing high‐dose (7 × 1015 cm−2) arsenic implants under various conditions. It is shown that detailed consideration of the initial electrical activation immediately after damage annealing, as well as the ramp‐up and ‐down conditions, is necessary in order to model the diffusion and electrical activation of the arsenic. The various stages of the annealing process are described, and the cumulative effect of each stage in the cycle on the final degree of electrical activation is discussed in the context of experimental results and dynamics of arsenic clustering and declustering.

The combined effects of band-to-band tunneling and impact ionization in the off regime of an LDD MOSFET

Fully self-consistent two-dimensional simulation of band-to-band tunneling (BTBT) in a lightly doped drain (LDD) MOSFET is reported. The simulation results are compared to experimental data and explain the observed current leakage effects. At low drain bias the leakage currents in the off regime can be explained by BTBT alone. At high drain bias and at deep subthreshold gate bias the leakage current is increasingly due to avalanche generation by carriers created initially in BTBT and accelerated subsequently in the high electric fields.<<ETX>>

Reverse short channel effect and channel length dependence of boron penetration in PMOSFETs

The anomalous increase in reverse-short-channel effect of PMOSFETs, in the presence of boron penetration from the gate, is examined here. Based on an extensive simulation and experimental study, we demonstrate that the degree of boron penetration is a function of the channel length and that long channel transistors are more susceptible to boron penetration compared to short channel devices. This leads to the observed decrease in threshold voltage with increasing channel length and hence, an enhanced reverse-short-channel-like behavior in PMOSFETs. Using length scale arguments, we propose that silicon interstitial absorption into the gate oxide is responsible for blocking boron penetration at the edges of the channel as compared to the middle, thus making the short channel length transistors more immune to boron penetration as compared to long channel length ones.

50-nm fully depleted SOI CMOS technology with HfO/sub 2/ gate dielectric and TiN gate

In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO/sub 2/ gate dielectric at the 50-nm physical gate length. Symmetric V/sub T/ is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I/sub on/=500 /spl mu/A//spl mu/m and I/sub off/=10 nA//spl mu/m at V/sub DD/=1.2 V for nMOSFET and I/sub on/=212 /spl mu/A//spl mu/m and I/sub off/=44 pA//spl mu/m at V/sub DD/=-1.2 V for pMOSFET, with a CET=30 /spl Aring/ and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V/sub DD/=1.2 V are also realized.