Tathagato Rai Dastidar

A synthesis system for analog circuits based on evolutionary search and topological reuse

We present a method for automated synthesis of analog circuits using evolutionary search and a set of circuit design rules based on topological reuse. The system requires only moderate expert knowledge on part of the user. It allows circuit size, circuit topology, and device values to evolve. The circuit representation scheme employs a topological reuse-based approach-it uses commonly used subcircuits for analog design as inputs and utilizes these to create the final circuit. The connectivity between these blocks is governed by a well-defined set of rules and the scheme is capable of representing most standard analog circuit topologies. The system operation consists of two phases-in the first phase, the circuit size and topology are evolved. A limited amount of device sizing also occurs in this phase. The second phase consists entirely of device value optimization. The design of the evaluation function-which evaluates each generated circuit using SPICE simulations-has also been automated to a great extent. The evaluation function is generated automatically depending on a behavioral description of the circuit. We present several experimental results obtained using this scheme, including two types of comparators, two types of oscillators, and an XOR logic gate. The generated circuits closely resemble hand designed circuits. The computational needs of the system are modest.

A verification system for transient response of analog circuits using model checking

Conventional temporal logics like CTL (Clarke et al., 2000), used for specifying properties of digital systems are not well suited for property specification of analog systems. We present a new temporal logic for specifying properties of analog circuits. We call this logic Ana CTL (CTL for analog circuit verification). It is shown that Ana CTL is more suitable for specifying properties of analog systems than other temporal logics. The application of Ana CTL for verification of transient behavior of arbitrarily nonlinear analog circuits has been presented. The transient response of a circuit under all possible input waveforms is represented as a finite state machine (FSM), by bounding and discretizing the continuous state space of an analog circuit This FSM is created by means of repeated SPICE simulations. Algorithms have been developed to run Ana CTL queries on this discretized model. The structure of this FSM is well suited to represent the characteristics of analog circuits, and enables us to run complex queries including real-time constraints in polynomial time. The application of these methods on several real life analog circuits has been presented and we show that this system is a useful aid for detecting and debugging design errors.

A verification system for transient response of analog circuits

We present a method for application of formal techniques like model checking and equivalence checking for validation of the transient response of nonlinear analog circuits. We propose a temporal logic called Ana CTL (computational tree logic for analog circuit verification) which is suitable for specifying properties specific to analog circuits. The application of Ana CTL for validation of transient behavior of arbitrarily nonlinear analog circuits is presented. The transient response of a circuit under all possible input waveforms is represented as a finite state machine (FSM), by bounding and discretizing the continuous state space of an analog circuit. We have developed algorithms to run Ana CTL queries on this discretized model using search-based methods which reduce the runtime considerably by avoiding creation of the whole FSM. The application of these methods on several real-life analog circuits is presented and we show that this system is a useful aid for detecting and debugging early design errors. We also present methods for checking the equivalence of transient response of two analog circuits. The behavior of two different analog circuits can rarely be exactly similar. Hence, we introduce a notion of approximate equivalence. A query language for checking different notions of user-definable approximate equivalence is presented which extends the syntax of the Ana CTL model checking language. In its extended form, Ana CTL can be used combining model checking with equivalence checking.

A methodology for efficient design of analog circuits using an automated simulation based synthesis tool

We present a methodology for efficient design of analog circuits using an automated simulation based synthesis tool. In this methodology, the designer chooses a suitable circuit topology and defines the performance criteria of the circuit. The synthesis tool provides optimized device dimensions which guarantees that the circuit meets the specified performance criteria across process corners. This methodology is independent of the circuit type (as long as the performance criteria can be quantified and measured from simulation data), the fabrication process being used, and also the circuit simulator of choice. We show that this design methodology reduces the design cycle time by a significant amount and helps analysing the trade off between different performance criteria. It also helps in analysing the suitability of several alternative topologies for a given purpose in a short time. In this paper we substantiate this claim with the help of an operational amplifier design.

A new device level digital simulator for simulation and functional verification of large semiconductor memories

Increasing use of embedded memories in modern day system-on-chip (SoC) designs escalates the need for CAD tools for effective functional verification of memories. We present a new simulator called Natsim for device level digital circuits which can be effectively used for simulation and functional verification of large semiconductor memories and other custom digital circuits. SPICE or switch-level Verilog cannot be effectively used for simulation of memories. Conventional switch level simulators like IRSIM [Salz, 1989], too, typically fail when used for simulating memory circuits, especially SRAM circuits, due to some inherent limitations in their voltage and delay calculation algorithms. We present a technique for voltage and delay calculation which is more robust than the method employed by earlier simulators. We also present a heuristic approach to predict the final logic value at a node in the circuit in presence of MOS transistors with unknown potentials at their gates. We present a methodology for functional verification of memories using Natsim. Experimental results for a wide range of memory circuits have been presented. The work presented in this paper is pending US patent.