Tatsuhiko Demura

A single-chip MPEG2 video decoder LSI

This MPEG2 video decoder LSI decodes MPEG2 standard bit streams. The compression algorithm in the MPEG2 is based on discrete cosine transform (DCT), variable length coding, and motion compensation similar to the MPEG1, the earlier standard. However, the processing speed should be more than four times faster than MPEG1. Moreover, several algorithms and structures to handle interlaced pictures are added to the MPEG1 standard. This LSI decodes in real time all motion-compensation modes and picture structures in MPEG2 bit streams of not only CCIR601 but also HDTV resolution.<<ETX>>

A video codec LSI for high-definition TV systems with one-transistor DRAM line memories

A video codec LSI for high-definition television (HDTV) systems has been developed. By using a time-compressed integration encoding technique, it converts a 20.0-MHz bandwidth luminance signal and two 5.0-MHz chrominance signals into a compressed image signal at 48.6-MHz sampling frequency. It is useful in many HDTV application systems, such as 400-Mb/s digital transmission system, a video disk player system, or an analog transmission system. Over 288000 elements, including a 52-kb one-transistor DRAM (dynamic random access memory) line memory specially developed for this LSI, were integrated on a 12.16*12.10-mm/sup 2/ chip. A standard cell layout method and a 1.2- mu m CMOS logic LSI process were used. >

New address-generation-unit architecture for video signal processing

This paper describes a new address generation unit (AGU) architecture for video signal processing. The proposed AGU has several sophisticated addressing modes obtained by analyzing many video signal processing algorithms, and can generate image memory addresses needed in video signal processing. This AGUs architecture was employed in a DSP being developed at present. In this paper, first of all, the architecture of the DSP and the role of the AGU are presented. Furthermore, the details of this AGU, such as the control method, addressing modes, and operations of the AGU in some typical applications are described.

A floating-point cell library and a 100-Mflops image signal processor

A new floating point macro cell library, suitable for logic synthesis of image signal processor, has been developed. A floating point Arithmetic Logic Unit(ALU), a floating point multiplier(MPY), an instruction RAM and a data register file are included in the library. The ALU and MPY can support not only IEEE754 floating point operations, but also fixed point operations and logical operations which are often used in image signal processing. They can operate at 33MHz clock cycle with three stage pipeline configuration. A new algorithm for calculation of absolute value is implemented in the ALU to get such a high speed operation. A new type of Vector Processor was synthesized with logic synthesis system. It has peak performance of 100MFLOPS at 33MHz, and it is suitable for large scale image processing, such as FFT, DCT, VQ and so on. High Speed 1.2 micron CMOS fabrication technology was used. In this paper, the details of the new algorithm used in the floating point ALU are discussed. Each component of the library and the synthesized Vector Processor is also described.

A new DSP architecture suited for image analysis

A DSP architecture suited for processing in the field of image analysis, which is placed between image preprocessing and image understanding, is described. The DSP, consisting of a flexible EU (execution unit) and hardwired AGUs (address generation units) with several well-considered addressing modes, achieved flexible capability for various algorithms in the image analysis field without complex sequence control. A programmable PLL which can generate the internal clock signal with high frequency has been implemented, and high performance has been achieved in cases of intensive calculations.<<ETX>>