Chikahiro Hori

Interleaving based variable ordering methods for ordered binary decision diagrams

Ordered binary decision diagrams (OBDDs) are efficient representations of Boolean functions and have been widely used in various computer-aided design tools. Since the size of an OBDD depends on variable ordering, it is important to find a good variable order for the efficient manipulation of OBDDs. In particular, it is important to find the same good variable order for multiple functions, since multiple functions are handled at the same time in most computer-aided design tools. The paper describes new variable ordering algorithms for multiple output circuits. The new algorithms use variable interleaving, while conventional algorithms use variable appending. For some benchmark circuits, OBDDs have been successfully generated by using the new algorithms, while they have not been generated by using conventional algorithms. Consequently, the new variable ordering algorithms are effective and allow us to apply OBDD-based CAD tools to wider classes of circuits.

A floating-point cell library and a 100-Mflops image signal processor

A new floating point macro cell library, suitable for logic synthesis of image signal processor, has been developed. A floating point Arithmetic Logic Unit(ALU), a floating point multiplier(MPY), an instruction RAM and a data register file are included in the library. The ALU and MPY can support not only IEEE754 floating point operations, but also fixed point operations and logical operations which are often used in image signal processing. They can operate at 33MHz clock cycle with three stage pipeline configuration. A new algorithm for calculation of absolute value is implemented in the ALU to get such a high speed operation. A new type of Vector Processor was synthesized with logic synthesis system. It has peak performance of 100MFLOPS at 33MHz, and it is suitable for large scale image processing, such as FFT, DCT, VQ and so on. High Speed 1.2 micron CMOS fabrication technology was used. In this paper, the details of the new algorithm used in the floating point ALU are discussed. Each component of the library and the synthesized Vector Processor is also described.

Design of a 32 bit microprocessor, TX1

Implementation of the TX1 VLSI microprocessor is described. Particular emphasis is placed on the design method, which meets the requirements of short design time with reasonable chip size. A one-phase clock system, which is a better solution for high-speed operation but requires careful design for evading the skew problem, is discussed. Design for testability is embedded in the chip. The TX1 is fabricated with a 1.0 mu m two-layer metal CMOS process. The chip contains 450 K transistors in a 10.89*10.27 mm/sup 2/ die. >