Tomoji Takada

A video codec LSI for high-definition TV systems with one-transistor DRAM line memories

A video codec LSI for high-definition television (HDTV) systems has been developed. By using a time-compressed integration encoding technique, it converts a 20.0-MHz bandwidth luminance signal and two 5.0-MHz chrominance signals into a compressed image signal at 48.6-MHz sampling frequency. It is useful in many HDTV application systems, such as 400-Mb/s digital transmission system, a video disk player system, or an analog transmission system. Over 288000 elements, including a 52-kb one-transistor DRAM (dynamic random access memory) line memory specially developed for this LSI, were integrated on a 12.16*12.10-mm/sup 2/ chip. A standard cell layout method and a 1.2- mu m CMOS logic LSI process were used. >

A triple-level wired 24K-gate CMOS gate array

A 24K-gate CMOS gate array has been developed using triple-level wiring and a hierarchical layout method. A typical delay time is 1.6 ns with a fanout of 3 and a 3-mm metal interconnect length. The master chip was designed to be freely divided into blocks. A previously developed digital signal processor has been realized on the array. The design time was reduced to 25% of the normal design cycle although the chip size is 3.3 times larger than was realized by a handcrafted design.

New address-generation-unit architecture for video signal processing

This paper describes a new address generation unit (AGU) architecture for video signal processing. The proposed AGU has several sophisticated addressing modes obtained by analyzing many video signal processing algorithms, and can generate image memory addresses needed in video signal processing. This AGUs architecture was employed in a DSP being developed at present. In this paper, first of all, the architecture of the DSP and the role of the AGU are presented. Furthermore, the details of this AGU, such as the control method, addressing modes, and operations of the AGU in some typical applications are described.

A floating-point cell library and a 100-Mflops image signal processor

A new floating point macro cell library, suitable for logic synthesis of image signal processor, has been developed. A floating point Arithmetic Logic Unit(ALU), a floating point multiplier(MPY), an instruction RAM and a data register file are included in the library. The ALU and MPY can support not only IEEE754 floating point operations, but also fixed point operations and logical operations which are often used in image signal processing. They can operate at 33MHz clock cycle with three stage pipeline configuration. A new algorithm for calculation of absolute value is implemented in the ALU to get such a high speed operation. A new type of Vector Processor was synthesized with logic synthesis system. It has peak performance of 100MFLOPS at 33MHz, and it is suitable for large scale image processing, such as FFT, DCT, VQ and so on. High Speed 1.2 micron CMOS fabrication technology was used. In this paper, the details of the new algorithm used in the floating point ALU are discussed. Each component of the library and the synthesized Vector Processor is also described.

A one-day chip: an innovative IC construction approach using electrically reconfigurable logic VLSI with on-chip programmable interconnections

A new custom IC design methodology and the associated logic VLSI chip, which offer an ultimately fast turnaround-time logic IC construction method, are proposed. The chip contains various kinds of logic functional blocks, such as inverters, NORs, NANDs, flip-flops, shift registers, counters, adders, multiplexers, and ALUs. Up to 200 SSI/MSI standard logic blocks can be provided. The E/SUP 2/PROM-type MOSFET switch matrix is adjacent to the functional blocks, in order to connect any output to specific inputs of the functional blocks. It also offers a ready-to-test aid, obtained by monitoring the signal waveform developed inside the chip. These features have the advantage over the present custom IC design methods (gate array, standard cell, silicon compiler, programmable logic array) that the designer can easily redesign the logic to obtain a digital system in an IC in a single day.

A new DSP architecture suited for image analysis

A DSP architecture suited for processing in the field of image analysis, which is placed between image preprocessing and image understanding, is described. The DSP, consisting of a flexible EU (execution unit) and hardwired AGUs (address generation units) with several well-considered addressing modes, achieved flexible capability for various algorithms in the image analysis field without complex sequence control. A programmable PLL which can generate the internal clock signal with high frequency has been implemented, and high performance has been achieved in cases of intensive calculations.<<ETX>>

A codec LSI for HDTV signals

The authors describe a codec LSI for a time-compressed-integration (TCI-) format high-definition TV (HDTV) signal. The chip converts a luminance signal sampled at 48.6 MHz and two chrominance signals sampled at 12.15 MHz into a TCI format signal at 48.6-MHz frequency and vice versa. The LSI employs a codec architecture to be used as a TCI encoder or decoder in one chip with minimum hardware and contains a PLL (phase-locked-loop) control circuit for clock synchronization in the decoder mode. It has three modes of operation corresponding to three HDTV systems, namely an analog transmission system, a 400-Mb/s digital transmission system, and a video disk player. The PLL control circuit executes a specific operation in each mode. The 48.6-MHz TCI or Y-signal is divided into two 24.3-MHz signals and applied to the LSI, thus allowing TTL (transistor-transistor logic) ICs to be used for the peripheral circuits. The chip was fabricated with a 1.2- mu m p-well CMOS and double-level Al interconnection technology. About 288 k elements, including a 52-kbit 1-Tr DRAM, are integrated in a 12.16-mm*12.10-mm die, mounted in a 209-pin pin-grid-array package.<<ETX>>