Tatsuya Goto

Advanced Method for Measuring Ultra-Low Contact Resistivity Between Silicide and Silicon Based on Cross Bridge Kelvin Resistor

In order to evaluate low contact resistivity precisely, we have developed a new test structure based on cross bridge Kelvin resistor. In this structure, the misalignment margin can be as small as possible. Furthermore, we had successively derived the theoretical expressions to ensure the validity of the newly developed method. This method will enable us to evaluate the silicide to silicon contact resistivity in the sub-10-8 ¿cm2 region.

Wide-range and precise tissue impedance analysis circuit with ultralow current source using gate-induced drain-leakage current

This paper presents a bioelectrical impedance analysis circuit with ultralow-current source using gate-induced drain-leakage (GIDL) current for biomedical applications. The proposed circuit consists of an ultralow-current reference circuit, a minimal voltage measurement block, a precise current source block, and a digital control logic circuit. The reference circuit generates pico-ampere-order currents based on GIDL current of an n-channel MOSFET. Fabricated in a 0.18μm 1P6M standard CMOS technology, the impedance analysis circuit occupies 0.27mm2 and can measure impedance range from 100Ω to 10MΩ. Experimental results shows that the fabricated current source using GIDL current generates a quite stable ultralow-current of 50pA, 100pA and 200pA, respectively. In addition, the proposed analysis circuit successfully measures the electrode-tissue interface impedance and tissue impedance by functional verification using monolayer and inhomogeneous agarose gel test setup phantom.

Impact of Tungsten Capping Layer on Yttrium Silicide for Low Resistance Source/Drain Contacts

Source/drain parasitic resistance RSD of MISFETs is a serious problem because it will limit their performance when the current drivability increases sufficiently. In order to reduce RSD, it is important to reduce contact resistance. As the Schottky Barrier Height (SBH) between silicide and silicon must be low to achieve low contact resistivity [1], a dual silicide structure, using low work function silicides for n silicon and high work function silicides for p silicon, is a promising solution [2]. However, it is difficult to obtain low SBH for electrons because it requires handling low work function metals, which are easily oxidized in air. Therefore, the oxidation prevention technology is indispensable. In this paper, we investigated the physical and electrical properties of tungsten/yttrium stack.