Tadahiro Ohmi

A small-area high-performance 512-point 2-dimensional FFT single-chip processor

A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource saving multi-datapath radix-2/sup 2/ computation element. The 2-stage CMA, including a pair of single-port SRAMs, is also introduced to speedup the execution time of the 2-dimensional FFTs. Using the above techniques, we have designed an FFT processor core which integrates 552,000 transistors within an area of 2.8 /spl times/ 2.8 mm/sup 2/ with CMOS 0.35 /spl mu/m triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensional FFT in 23.2 /spl mu/sec and a 2-dimensional one in only 23.8 msec at 133 MHz operation.

An image recognition processor using dynamically reconfigurable ALU

An image recognition processor, utilizing a phase only correlation (POC) algorithm is proposed. The arithmetic logical unit (ALU) in this processor can be re-configured dynamically. By arranging the POC algorithm to a form suitable for reconfigurable computing, the proposed processor can perform 2D 512/spl times/512 pixel image recognition within 105.2 ms and using 310.9 mW of power. This power consumption is 11.3 times lower than that of a previously reported work with same execution time.

A Fine-Grained Programmable Logic Module with Small Amount of Configuration Data for Dynamically Reconfigurable Field-Programmable Gate Array

Dynamically customizable and reconfigurable hardware architecture for a specific task on demand is one of the most important issues to bring out a novel-computing paradigm in the era of system LSIs. Our target is to realize a flexible processor which is a kind of dynamically reconfigurable field-programmable gate array (FPGA) and is able to execute signal processing while reading the next configuration data (CD) simultaneously. In order to realize the flexible processor, since the amount of CD is enormous in conventional FPGAs, it is necessary to reduce the amount of CD as much as possible. In this paper, we propose a newly developed programmable logic module that can reduce the amount of CD to no less than 86% of that for the conventional Look Up Table (LUT)-based programmable logic module.

A dynamically-reconfigurable image recognition processor

Summary form only given. We introduce a new image recognition processor using a run-time reconfiguration (RTR) technology. A phase impulse response function (PIRF) is employed as an application for evaluating the performance of RTR architecture. By utilizing the RTR architecture effectively, a complicated image processing application such as PIRF can be implemented on a single processor. To achieve this, a dynamically-reconfigurable arithmetic logic unit (DRALU) is proposed. Simulation results show that our proposed processor using DRALU can execute the PIRF within 30 msec.

The Flexible Processor-dynamically reconfigurable logic array for personal-use emulation system

A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for single chip emulation system is developed. It demonstrates the sequential execution of sub-circuits divided from original circuit, by newly developed Temporal Communication Module (TCM). In order to accelerate emulation speed, a logic element, which can reduce configuration data by 30% as compared to conventional Look-Up-Table, is implemented. The chip (3.9/spl times/3.9 mm/sup 2/) fabricated with 0.6 /spl mu/m CMOS technology operates at 33 MHz with 5.0 V power supply.

Flexible Processor Based on Full-Adder/D-Flip-Flop Merged Module (FDMM)

A flexible processor based on the full-adder/D-flip-flop merged module (FDMM) has been proposed and fabricated. The developed FDMM has a unique ability to perform both logic and flip-flop functions with a small number of transistors by merging the common parts of both circuits, which will improve hardware efficiency. We have also developed a context memory block (CMB) to reconfigure the hardware dynamically. It enables us to write the next configuration in parallel into the flexible processor during processing, which reduces the overhead of actual reconfiguration time and improves the performance.

An approach to realize time-sharing of flip-flops in time-multiplexed FPGAs

This work introduces a new approach to realize timesharing of flip-flops in time-multiplexed FPGAs. In order to implement large circuits in time-multiplexed FPGAs, it is important that flip-flops, as well as combinational logics, must be time-shared efficiently. To handle sequential circuits, previous works either required large amount of communication between sub-circuits or caused storage overhead due to buffer usage, resulting to complicated placing and routing tasks and limiting the size of target circuit that can be implemented. We propose a simple algorithm that can efficiently realize timesharing of flip-flops by refining an initial partitioning. Experimental results show that implementation of our approach can eliminate all storage overhead while the resultant change in the amount of communication between sub-circuits can be kept less than /spl plusmn/4%. We have also designed and fabricated a new temporal communication module, and implemented our new approach on it.

The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developed. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit. In order to accelerate emulation speed, a logic element, reducing total configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support save/restore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible Processor.

A dynamically reconfigurable IP for data-intensive applications

In this paper, we introduce a report on designing an ASIC which includes a dynamically reconfigurable IP that can change composition within a clock cycle. Empirical design TAT evaluations were made and the results showed that a data-intensive processor equipped with this IP can be designed in 4 weeks.