Akinobu Teramoto

Dependence of electron channel mobility on Si-SiO/sub 2/ interface microroughness

The effect of the Si-SiO/sub 2/ interface microroughness on the electron channel mobility of n-MOSFETs was investigated. The surface microroughness was controlled by changing the mixing ratio of NH/sub 4/OH in the NH/sub 4/OH-H/sub 2/O/sub 2/-H/sub 2/O solution in the RCA cleaning procedure. The gate oxide was etched, following the evaluation of the electrical characteristics of MOS transistors, to measure the microroughness of the Si-SiO/sub 2/ interface with scanning tunneling microscopy (STM). As the interface microroughness increases, the electron channel mobility, which can be obtained from the current-voltage characteristics of the MOSFET, gets lower. The channel mobility is around 360 cm/sup 2//V-s when the average interface microroughness is 0.2 nm, where the substrate impurity concentration is 4.5*10/sup 17/ cm/sup -3/, i.e. the electron bulk mobility is 400 cm/sup 2//V-s. It goes down to 100 cm/sup 2//V-s when the interface microroughness exceeds 1 nm.<<ETX>>

New era of silicon technologies due to radical reaction based semiconductor manufacturing

Current semiconductor technology, the so-called the molecule reaction based semiconductor manufacturing, now faces a very severe standstill due to the drastic increase of gate leakage currents and drain leakage currents. Radical reaction based semiconductor manufacturing has been developed to completely overcome the current standstill by introducing microwave excited high density plasma with very low electron temperatures and without accompanying charge-up damage.The introduction of radical reaction based semiconductor manufacturing has made it possible to fabricate LSI devices on any crystal orientation Si substrate surface as well as (100) Si substrate surfaces, and to eliminate a very severe limitation to the antenna ratio in the circuit layout patterns, which is strictly limited to less than 100–200 in order to obtain a relatively high production yield.

High Permeability and Low Loss Ni–Fe Composite Material for High-Frequency Applications

A magnetic material with high permeability and low loss characteristics at high frequency is required for miniaturizing electronic components such as antennas. The key factors to keeping low magnetic loss are a high magnetic resonance frequency and the suppression of the eddy currents. We have fabricated a low-loss magnetic composite material by dispersing Ni 78Fe22 (permalloy) fine flakes in polymers; the thickness of the flakes was less than skin depth. The magnetic loss decreased with increased stirring time, and the minimum value occurred when the agglomerated particles decreased and most of the particles were deformed into flakes. Moreover, Zn5Ni75Fe20 composite material indicated high permeability when the flakes were oriented in the direction of sheets. The effect of wavelength shortening by permeability enhancement and the low loss characteristic were confirmed by experimental results of a rod antenna loaded with the developed magnetic composite material.

Very High Carrier Mobility for High-Performance CMOS on a Si(110) Surface

In this paper, we demonstrate CMOS characteristics on a Si(110) surface using surface flattening processes and radical oxidation. A Si(110) surface is easily roughened by OH- ions in the cleaning solution compared with a Si(100) surface. A flat Si(110) surface is realized by the combination of flattening processes, which include a high-temperature wet oxidation, a radical oxidation, and a five-step room-temperature cleaning as a pregate-oxidation cleaning, which does not employ an alkali solution. On the flat surface, the current drivability of a p-channel MOSFET on a Si(110) surface is three times larger than that on a Si(100) surface, and the current drivability of an n-channel MOSFET on a Si(100) surface can be improved compared with that without the flattening processes and alkali-free cleaning. The 1/f noise of the n-channel MOSFET and p-channel MOSFET on a flattened Si(110) surface is one order of magnitude less than that of a conventional n-channel MOSFET on a Si(100) surface. Thus, a high-speed and low-flicker-noise p-channel MOSFET can be realized on a flat Si(110) surface. Furthermore, a CMOS implementation in which the current drivabilities of the p-channel and n-channel MOSFETs are balanced can be realized (balanced CMOS). These advantages are very useful in analog/digital mixed-signal circuits.

Very thin oxide film on a silicon surface by ultraclean oxidation

Very thin oxide films with a high electrical insulating performance have been grown by controlling preoxide growth using the ultraclean oxidation method. The current level through the ultraclean oxide is lower than that through the conventional dry oxide including thicker preoxide. The barrier height at the silicon‐oxide interface for electrons emission from silicon to oxide for the ultraclean oxide is little decreased as the thickness is thinner, while the barrier height for conventional dry oxide is drastically decreased. The growth rate of ultraclean oxide at 900 °C is governed by a simple parabolic law even in the range of 5–20 nm.

Atomically Flat Silicon Surface and Silicon/Insulator Interface Formation Technologies for (100) Surface Orientation Large-Diameter Wafers Introducing High Performance and Low-Noise Metal–Insulator–Silicon FETs

Technology to atomically flatten the silicon surface on (100) orientation large-diameter wafer and the formation technology of an atomically flat insulator film/silicon interface are developed in this paper. Atomically flat silicon surfaces composed of atomic terraces and steps are obtained on (100) orientation 200-mm-diameter wafers by annealing in pure argon ambience at 1200degC for 30 min. Atomically flat surfaces with various terrace widths and step structures are observed by atomic force microscopy. It is found that the atomic terrace width changes widely with an off angle of the wafer surface from the (100) lattice plane. It is also found that the direction of the off angle significantly affects the atomically flat surface morphology, i.e., when the directions of the off angles are parallel to the <110> directions, the step structure is composed of alternating pairs of straight and triangular steps. When the directions of the off angles are parallel to the <100> directions, the step structure is composed of only straight steps. By precise control of the off angle and the direction toward the <100> directions for a 200-mm-diameter silicon wafer, we have succeeded in fabricating an atomically flat surface with straight atomic steps and a very uniform terrace width of 140-150 nm on the entire surface of a large-diameter silicon wafer. Furthermore, it is found that only radical-reaction-based insulator film formation technology, such as oxidation utilizing oxygen radicals carried out at a low temperature (400degC ), preserves the atomic flatness of the insulator film/silicon interface. Finally, when MOSFETs are fabricated with an atomically flat interface, they exhibit near ideal subthreshold swing factors, with much smaller fluctuation, extremely lower 1/f noise, and higher MOS dielectric breakdown field intensity compared with MOSFETs fabricated with conventional technologies.

Revolutional Progress of Silicon Technologies Exhibiting Very High Speed Performance Over a 50-GHz Clock Rate

Current silicon technologies are now facing very severe standstill, i.e., the operation speed is strictly limited at a clock rate of about 3.8 GHz due to the limitation of the thinning of the gate insulator film thickness because of its large amount of leakage currents through the current thermal oxide films. This typical disadvantage of current silicon technologies has been completely overcome by introducing the newly developed radical-reaction-based semiconductor manufacturing instead of the current molecule-reaction-based semiconductor manufacturing, i.e., direct nitridation films such as Si3N 4 where the gate leakage current through the insulator films has been confirmed to be decreased by a factor of at least three orders of magnitude. The speed performance of silicon large-scale integrations is enhanced to exhibit a clock rate of more than 50 GHz by introducing the balanced complementary MOS on a silicon (551) surface substrate using 3-D-structured MOS transistors, where new key technologies must be introduced, namely: 1) direct nitridation gate insulator film Si3 N4 for 3-D MOS transistors; 2) atomic-order flat-gate insulator film/silicon interface; 3) drastically decreased series resistance of the source and drain electrodes by a factor of two orders of magnitude; and 4) introduction of the accumulation-mode MOS transistors instead of the inversion-mode MOS transistors

Impact of Improved High-Performance Si(110)-Oriented Metal?Oxide?Semiconductor Field-Effect Transistors Using Accumulation-Mode Fully Depleted Silicon-on-Insulator Devices

In this study, we focus on the improved device characteristics of fully depleted silicon-on-insulator (FD-SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) on a Si(110) surface using normally off accumulation-mode device structures. It is demonstrated that the current drivability of an accumulation-mode FD-SOI n-MOSFET on Si(110) is about 1.5 times larger than that of a conventional inversion-mode FD-SOI n-MOSFET on a (110)-oriented surface. Furthermore, it is confirmed that the current drivability of an accumulation-mode FD-SOI p-MOSFET fabricated on Si(110) is also 3 times larger than that of a conventional FD-SOI pMOS formed on a Si(100) surface.

1/f noise suppression of pMOSFETs fabricated on Si(100) and Si(110) using an alkali-free cleaning process

This paper reports that the low-frequency noise in p-channel MOSFETs fabricated on [110] and (100) crystallographic oriented silicon is related to the microroughness of the silicon surface. Since the conventional RCA cleaning process makes the surface rough, especially in the case of [110] orientation, the authors developed the so-called 5-step room temperature cleaning process that does not use alkaline solution. The combination of this new cleaning process with the microwave-excited high-density plasma oxidation process for the formation of the gate oxide, instead of the standard 900/spl deg/C thermal oxidation process, leads to a reduction of the microroughness and a drop in the 1/f noise level of more than one decade. Furthermore, this reduction is not only observed for the [110] orientation but also seen, albeit to a much lesser extent, for (100) if it is treated in the same way.

High-Speed Damage-Free Contact Hole Etching Using Dual Shower Head Microwave-Excited High-Density-Plasma Equipment

Dual shower head microwave-excited plasma etching equipment for separating the plasma-excited region from the etching process region has been developed. With the aim of realization of damage-free etching, the carrier activation of boron-doped p+-Si is investigated after plasma irradiation. The damage-free-etching mode in which holes do not deactivate was found. Contact holes are successfully etched using a surface damage-free etching process consisting of high-speed etching mode and surface damage-free etching mode. The damage-free-etching mode consists of low-self-bias condition and a low etching gas flow rate as compared with the high-speed mode. For both modes, the etcher can maintain the process uniformity because the etcher can control self-bias voltages without changing other process parameters.