Michiko Takei

High performance poly-Si TFTs on a glass by a stable scanning CW laser lateral crystallization

We have developed high performance poly-Si TFTs, which have comparable performance to that of [100] Si-MOSFETs, by using a stable scanning DPSS CW laser lateral crystallization without introduction of thermal damage to 300/spl times/300 mm/sup 2/ glass substrates with process temperature below 450/spl deg/C.

High-performance polycrystalline silicon thin film transistors on non-alkali glass produced using continuous wave laser lateral crystallization

We have developed high-performance polycrystalline silicon (poly-Si) thin film transistors (TFTs) with a field-effect mobility of 566 cm2/Vs for n-channel TFT and 200 cm2/Vs for p-channel TFT on 300 mm×300 mm non-alkali glass substrate. The TFTs were developed using a stable diode pumped solid state (DPSS) continuous-wave laser lateral crystallization (CLC) method at a temperature below 450°C. The high performance of the TFTs was attributed to the very large predominantly (100)-oriented grain. This crystallization method will enable high-performance Si-LSI circuits to be fabricated on large non-alkali glass substrates.

High Performance Low Temperature Polycrystalline Silicon Thin Film Transistors on Non-alkaline Glass Produced Using Diode Pumped Solid State Continuous Wave Laser Lateral Crystallization

High performance low temperature polycrystalline silicon (poly-Si) thin film transistors (TFTs) with large grains were created using diode pumped solid state (DPSS) continuous wave (CW) laser lateral crystallization (CLC), employing fabrication processes at 450°C. Field-effect mobilities of 566 cm2/Vs for the n-channel and 200 cm2/Vs for the p-channel were obtained for a thick Si film (100–150 nm) on a 300×300 mm non-alkaline glass substrate. The high performance of the TFTs is attributed to the predominantly (100)-oriented very large grains. With a decreasing Si-film thickness, the grain size decreases, and the surface orientation of the grain changes from (100) to other orientations. These effects lead to reduced field-effect mobility with decreasing Si-film thickness, but it is easy to obtain a high field-effect mobility of over 300 cm2/Vs, even with a 50 nm thick Si film, without special processing techniques. A complementary metal oxide semiconductor (CMOS) ring oscillator was fabricated using a thin Si film 65 nm thick to demonstrate the high circuit performance of CLC poly-Si TFTs by applying the simplest CMOS process technology. A delay of 400 ps/stage at a gate length of 1.5 µm and a supply voltage of Vdd=5.0 (V) was produced on a large non-alkaline glass substrate utilizing a fabrication temperature of 450°C. This crystallization method will lead to the fabrication of high-performance and cheap Si-LSI circuits on large non-alkaline glass substrates.

POLYCRYSTALLINE SILICON FORMED BY ULTRAHIGH-VACUUM SPUTTERING SYSTEM

Using an ultrahigh‐vacuum (UHV) sputtering system, we could grow two new methods of polycrystalline silicon films. The one is as‐deposited polycrystalline silicon on glass at substrate temperatures under 500 °C. The other is solid‐phase‐crystallization by thermal annealing of as‐deposited amorphous silicon films in a UHV. As‐deposited polycrystalline silicon films were oriented to (220) and grain sizes were determined from half‐width of x‐ray diffraction to be about 40 nm. From the deposition temperature dependence of the x‐ray diffraction peak intensity, the activation energy of the crystalline growth was calculated to be about 0.6 eV. Hydrogen atoms in the sputtering gas lower the reproducibility of as‐deposited poly‐Si. Polycrystalline silicon films produced by thermal annealing of as‐deposited amorphous silicon films at 550 °C in UHV have a (111) orientation. Field‐effect mobilities of the as‐deposited polycrystalline silicon film and the polycrystalline silicon film by UHV thermal annealing were 5 an...

NON-MASS-SEPARATED ION SHOWER DOPING OF POLYCRYSTALLINE SILICON

Practical polycrystalline silicon thin‐film transistors need a low‐temperature doping technique. Ion shower doping with a main ion source of P2Hx (x=1,2,...) was studied. This technique implants a molecule in the polycrystalline silicon surface with a low acceleration voltage. A critical impurity density from polycrystalline phase to amorphous phase for phosphorus in polycrystalline silicon of 2.0×1020 ions/cm3was found. Sheet resistance with ion shower doping was lower than with conventional ion implantation at low temperature. This is a result of an increase in sheet carriers, because the low‐temperature recovering of defects is done by molecular implantation and hydrogen atoms compensate defects. Implanted polycrystalline Si with a Hall mobility of 5 cm2/V s was obtained.

Grain-Boundary Related Hot Carrier Degradation Mechanism in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Unique degradation behavior of transfer characteristics was observed in low-temperature (LT) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) after hot carrier stress. In the transfer characteristics, drain current was reduced markedly after stress at a gate voltage (VG) of more than the threshold voltage (VT), while it showed little change after stress at VG of less than VT. These phenomena cannot be explained by the generation of fixed charges in the gate oxide or gate-oxide interface trap charges. To understand this degradation mechanism, the stress-induced resistance RI is introduced, which is connected with the channel resistance Rchannel in series. The calculated RI values are systematically decreased with the increase in drain voltage (VD), which indicates that the degraded region is close to the drain edge near the surface. Moreover, RI values show exponential decay with the increase in VG, which implies the lowering of a potential barrier. A possible origin of RI is potential barriers caused by negative charges generated at the grain boundaries degraded by hot carrier attack.

12.3: High Throughput CW-Laser Lateral Crystallization for Low-Temperature Poly-Si TFTs and Fabrication of 16 bit SRAMs and 270MHz Shift Registers

Throughput improvement and fabrications of 4×4 bit SRAMs and 270 MHz shift registers are described for the CW-Laser Lateral Crystallization (CLC) of amorphous-Si on glass substrate. For the pixel array, effective area-crystallization rate is improved to 48cm2/s for 171ppi and 68cm2/s for 119ppi by 16 sub-laser-beams and 2m/s scanning speed.

Characteristics of low-temperature poly-Si TFTs on Al/glass substrates

The low-temperature poly-Si TFTs described here were fabricated on the Al/glass substrates by anodic oxidation of Al. An Al layer on glass substrates can be used to control threshold voltage, improve stabilities, and suppress the temperature rise due to self-heating. The Al layer on glass, thus assuring the improved reliability of displays, using this type of TFT, effectively suppressed the self-heating effect of poly-Si TFTs on glass. The threshold voltage of a TFT with an Al layer was more stable than that without an Al layer. These results were supported by numerical analysis.

Self-aligned top and bottom metal double gate low temperature poly-Si TFT fabricated at 550/spl deg/C on non-alkali glass substrate by using DPSS CW laser lateral crystallization method

Self-aligned top and bottom metal double gate (SAMDG) low-temperature polycrystalline silicon (poly-Si) thin film transistors (TFTs) were fabricated at 550/spl deg/C using the diode pumped solid state (DPSS) CW laser lateral crystallization (CLC) method, on non-alkali glass. The current drivability of these TFTs is eight or nine times as large as that of conventional excimer laser crystallized (ELC) poly-Si TFTs. It was confirmed that the extreme high performance of SAMDG CLC poly-Si TFT was maintained for gate length of 2.0 /spl mu/m.

Implantation temperature effect on polycrystalline silicon by ion shower doping

We present a new doping technique using an ion shower doping system with a bucket ion source. Phosphorus atoms were implanted in polycrystalline silicon from room temperature to 300 °C. Sheet resistances were significantly reduced by raising the implantation temperature. With a crystal fraction of 85%, sheet resistance was 5×102 S−1/⧠ as implanted. These effects were not due to pure thermal annealing by ion beam heating. A significant improvement was found in sheet resistance as a result of averaging the impurity profile by radiation enhanced diffusion and low temperature recrystallization of the implanted region by collision of atoms.