Tatsuya Kanda

Synchronous DRAM whose power consumption is minimized

Memory device, memory controller and memory system

Semiconductor memory capable of transitioning from a power-down state in a synchronous mode to a standby state in an asynchronous mode without setting by a control register

Semiconductor memory device and method of controlling the same

Self-test circuit and memory device incorporating it

Write data input circuit

Mode register control circuit and semiconductor device having the same

Semiconductor device accepting data which includes serial data signals, in synchronization with a data strobe signal

Semiconductor device reconciling different timing signals

Memory device including a double-rate input/output circuit