Tatsuya Yokoyama

A high speed protocol processor to execute OSI

A high-speed open systems interconnection (OSI) protocol processor is described which is intended for use in LAN adapters. The processor uses recently developed hardware for normal data transfer on layer 2 (LLC class 1), layer 3 (CLNP) and layer 4 (TP4). Connection control and abnormal data transfer (i.e. error handling) of OSI are executed by a general purpose microprocessor. In an experimental system, this processor increased OSI processing speed seven to 12 times over conventional systems. The new processor can therefore significantly improve LAN adapter performance by reducing the overhead associated with OSI processing time.<<ETX>>

A high speed protocol processor to boost gateway performance

The authors propose a high-speed protocol processor for gateways based on the following concept: normal data transfer is executed by special-purpose hardware and a general-purpose microprocessor handles abnormal data transfer and connection control. To analyze the quantitative effect of this proposal, a high-speed protocol processor which can execute OSI (open systems interconnection) layers two to four was manufactured, and its performance was measured. The protocol processing time for normal data transfer in the experimental system is 1/12 that of the conventional system on the transmission side and 1/7 that of the conventional system on the reception side. This result shows that application of the high-speed protocol processor in protocol-converting gateways is effective for improving performance.<<ETX>>