Tetsuhiko Hirata

Flexible service creation node architecture and its implementation

With the spread of always-on forms of broadband-access, such as ADSL and FTTH, new content-delivery services have appeared. However, conventional network nodes are not capable of providing rapid content provision, because they have poor scalability and a lack of reliability. We propose a flexible service-creation node architecture, based on the following concepts. Scalability is achieved by inserting multiple functionally identical service modules into extensible function blocks; new functions are easily added by inserting modules with the appropriate new functionality, and a failure occurring in one module does not affect the other modules because they all work independently. A prototype system shows that this modular node architecture is effective in terms of performance scalability, functional flexibility, and reliability.

Testbed System of Inter-Radio System Switching for Cognitive Radio

The cognitive radio system consists of multiple wireless access systems that cover overlapping areas and cognitive terminals that use one or more of the wireless accesses simultaneously. In this paper, we describe the architecture of the cognitive radio system and the inter-system handover protocols. In the architecture, each cognitive terminal, which can access multiple radio systems, operates with a single local IP address. The control sequence and packet format are designed to achieve fast handover among the radio systems. Based on the architecture, we have developed a testbed system. On this system, we demonstrate that data can be delivered continuously and radio systems can be switched correctly without any packet loss. In addition, we present the result of the evaluation of the end-to-end latency on the testbed system. These testbed results demonstrate the system architecture described in the paper can achieve a cognitive radio system.

A high speed protocol processor to execute OSI

A high-speed open systems interconnection (OSI) protocol processor is described which is intended for use in LAN adapters. The processor uses recently developed hardware for normal data transfer on layer 2 (LLC class 1), layer 3 (CLNP) and layer 4 (TP4). Connection control and abnormal data transfer (i.e. error handling) of OSI are executed by a general purpose microprocessor. In an experimental system, this processor increased OSI processing speed seven to 12 times over conventional systems. The new processor can therefore significantly improve LAN adapter performance by reducing the overhead associated with OSI processing time.<<ETX>>

Simulation and Basic Experiment of Inter Radio System Handover for Cognitive Radio

Cognitive radio system consists of multiple wireless accesses that cover overlapping area, and cognitive terminals that use one or more of the wireless accesses simultaneously. In this paper, we propose the architecture of the cognitive radio system, and the inter-system handover protocols. In the proposed architecture, each cognitive terminal, that has multiple radio systems, operates with a single local IP address. The control sequence and packet format are designed to achieve fast handover among the radio systems. Based on the proposed architecture, we have developed both a simulator and a testbed system with WiMAX and wireless LAN. Through simulation and testbed, we have proved that stream data can be delivered continuously without any effects of the handover. Also, we present the evaluation result of the end-to-end latency on the testbed system.

A high speed protocol processor to boost gateway performance

The authors propose a high-speed protocol processor for gateways based on the following concept: normal data transfer is executed by special-purpose hardware and a general-purpose microprocessor handles abnormal data transfer and connection control. To analyze the quantitative effect of this proposal, a high-speed protocol processor which can execute OSI (open systems interconnection) layers two to four was manufactured, and its performance was measured. The protocol processing time for normal data transfer in the experimental system is 1/12 that of the conventional system on the transmission side and 1/7 that of the conventional system on the reception side. This result shows that application of the high-speed protocol processor in protocol-converting gateways is effective for improving performance.<<ETX>>

Proposal and Testbed System of Inter Radio System Switching for Cognitive Radio

Cognitive radio system consists of multiple wireless accesses that cover overlapping area, and cognitive terminals that use one or more of the wireless accesses simultaneously. In this paper, we propose the architecture of the cognitive radio system, and the inter-system handover protocols. In the proposed architecture, each cognitive terminal, that has multiple radio systems, operates with a single local IP address. The control sequence and packet format are designed to achieve fast handover among the radio systems. Based on the proposed architecture, we have developed a testbed system. On this system, we have proved that data can be delivered continuously and radio systems can be switched correctly without any packet loss. Also, we present the evaluation result of the end-to-end latency on the testbed system.