Tawfik Ismail

On the design of asynchronous optical packet switch architectures with shared delay lines and converters

Optical packet switching (OPS) is a promising technology to enable next-generation high-speed IP networks. A major issue in OPS is packet contention that occurs when two or more packets attempt to access the same output fiber. In such a case, packets may be dropped, leading to degraded overall switching performance. Several contention resolution techniques have been investigated in the literature including the use of fiber delay lines (FDLs), wavelength converters (WCs), and deflection routing. These solution typically induce extra complexity to the switch design. Accordingly, a key design objective for OPS is to reduce packet loss without increasing switching complexity and delay. In this paper, we investigate the performance of contention resolution in asynchronous OPS architectures with shared FDLs and WCs in terms of packet loss and average switching delay. In particular, an enhanced FDL-based and a novel Hybrid architecture with shared FLDs and WCs are proposed, and their packet scheduling algorithms are presented and evaluated. Extensive simulation studies show that the performance of proposed FDL-based architecture outperforms typical OPS architectures reported in the literature. In addition, it shown that, for the same packet loss ratio, the proposed hybrid architecture can achieve up to 30% reduction in the total number of ports and around 80% reduction in the overall length of fiber as compared to the FDL-based architectures.

Priority-select arbiter: An efficient round-robin arbiter

Round robin arbiter (RRA) is a critical block in nowadays designs. It is widely found in System-on-chips and Network-on-chips. The need of an efficient RRA has increased extensively as it is a limiting performance block. In this paper, we deliver a comparative review between different RRA architectures found in literature. We also propose a novel efficient RRA architecture. The FPGA implementation results of the previous RRA architectures and our proposed one are given, that show the improvements of the proposed RRA.

Performance analysis of SIM-DPSK FSO system over lognormal fading with pointing errors

In this paper, average bit error rate (BER) and outage probability are analysed in the free-space optical (FSO) system employing subcarrier intensity modulation (SIM) with differential phase shift keying (DPSK). The FSO channel is described by the lognormal atmospheric turbulence and the pointing error effects. Closed-form analytical expressions for the average BER and outage probability are proposed. Furthermore, the numerical results of the proposed form are presented and compered with the numerical solution of the integral form.

Comparative review of NoCs in the context of ASICs and FPGAs

Network-on-Chip (NoC) is an emerging solution for interconnect problems for both ASICs and FPGAs nowadays. In this paper, we deliver a comparative review between ASIC-based and FPGA-based NoCs. An exploration of design tradeoffs for different NoC design parameters is also given. We also propose an evaluation methodology and design recommendations for various design parameters for both ASIC and FPGA oriented NoCs. These design recommendations help in selecting the optimum design parameters according to the requirements of the application used.

Optical packet switching architecture using wavelength optical crossbars

All-optical packet switching (OPS) is one of the promising technologies for the next generation of optical networks. It realizes the packet switching in optical domain that eliminates optical-electrical and electrical- optical conversions. One of the main components in an OPS network is the optical interconnect that provides the basic functionality of directing packets from input ports to the desired output ports, while maintaining data in the optical domain. Advances in all-optical technologies enable the wavelength exchanging phenomenon that can be used to develop new optical interconnect architectures. These architectures simultaneously combine the switching and the conversion domains. Thus, the use of the exchanging technology reduces the complexity without impacting the overall switching performance. In this paper, a new bufferless OPS interconnect by adopting wavelength optical crossbars that can combine both switching and wavelength conversion capabilities is proposed. The proposed architecture can operate in either of two modes: blocking or nonblocking. Our analysis to the proposed architecture confirms that, for the same number of input and output ports, a reduction in conversion and switching complexity can reached up to 50% and 99%, respectively, compared to traditional architectures.

Wavelength exchanging technologies modeling, comparison, and validation

Simultaneous power exchange between two input signals, has been theoretically and experimentally demonstrated based on two phenomena: Four Wave Mixing (FWM) in High-Linear Dispersion Shifted Fiber (HNL-DSF) and Three Wave Mixing (TWM) in NonLinear Photonic Crystals (NL-PC). These phenomena have been used in many applications in WDM optical networks such as, wavelength conversion, wavelength sampling, optical 3R, optical interconnects and optical add-drop multiplexing. In this work, numerical simulation of the exchanging process is presented to compare the performance of using these components in WDM optical networks using MatIab-Simulink.

The impact of changing HNL-DSF parameters on wavelength exchanging

Integrated Fiber (IF) approach for optical signal processing offers significant advantages in both performance and cost when compared to conventional electrical processing. The main problem in optical single processing is to maintain the data in the optical domain without converting it to the electrical domain. Currently, many devices have been proposed for processing the data in the optical domain. The Wavelength Optical Crossbar (WOC), one of the important devices in optical networks, has been developed based on the phenomenon of wavelength exchanging. High-NonLinear Dispersion Shifted Fiber (HNL-DSF) provides a good performance due to the high mixing efficiency. In this paper, we will study the impacts of changing the HNL-DSF parameter on the wavelength exchanging.

A VCO-Based MPPT Circuit for Low-Voltage Energy Harvesters

Thermal energy harvesting has many key challenges such as getting a sufficient output power, while achieving maximum power efficiency from thermoelectric generators (TEGs). A new VCO-based MPPT circuit for low-power applications is introduced. The proposed MPPT circuit is used in conjunction with Pelliconi charge pump forming a low-power thermal energy harvesting system. This system models the temperature difference between TEG module layers by 0.25V that is boosted to 3V. A prototype is implemented using UMC 130nm technology process, which achieves 61.6 % power efficiency, with output voltage level approximately 3V at maximum load current of 60 µA.

An ultra-low power voltage-to-time converter (VTC) circuit for low power and low speed applications

An ultra-low power voltage-to-time converter (VTC) circuit is proposed. The VTC circuit is compatible with wide range of applications (i.e. sensors, integrated DC-DC voltage converters) especially for time-based analog-to-digital converters (T-ADCs). In T-ADCs, the input voltage signal is first converted into a delay pulse using the VTC circuit, then this delay signal is converted into a digital code through time-to-digital converter (TDC). The main advantages of the T-ADC are that it: 1) eliminates the need for pre-amplifier stages, 2) operates at low supply voltage, and 3) supports low-speed applications as well as high-speed applications. In this paper, two VTC architectures are presented: a single ended architecture, and a fully differential architecture. The core VTC architecture uses a modified current starved inverter biased in subthreshold to maintain low-power consumption level. A prototype of the proposed VTC is implemented in 130nm CMOS technology, it exhibits a nonlinearity of 1 % per 150-mV for single-ended architecture, while exhibits nonlinearity of ±0.4 % per 240-mV for the fully differential one.

Performance analysis of hybrid lossy/lossless compression techniques for EEG data

Long recording time, large number of electrodes, and a high sampling rate together produce a great data size of Electroencephalography (EEG). Therefore, more bandwidth and space are required for efficient data transmission and storing. So, EEG data compression is a very important problem in order to transmit EEG data efficiently with fewer bandwidth and storing it in a less space. In this paper, We use the Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) which are lossy compression methods in order to convert the randomness EEG data to high redundancy data. Therefore, adding a lossless compression algorithm after the lossy compression is a good idea to get a high compression ratio without any distortion in the signal. Here, we use Run Length Encoding (RLE) and Arithmetic Encoding which are lossless compression methods. Total times for compression and reconstruction (T), Compression Ratio (CR), Root Mean Square Error (RMSE), and Structural Similarity Index (SSIM) are evaluated in order to check the effectiveness of the proposed system.