Tenko Yamashita

High Performance 65nm SOI Transistors Using Laser Spike Annealing

In this paper we present enhancements in transistor performance and manufacturability of a high performance 65nm node SOI transistor by the combination of reduced RTA temperature and laser spike anneal (LTRTA+LSA) achieved through simultaneous optimization of offset spacer and extension/halo. DC NFET drive current is increased by 10% to a value of 1120 muA/mum (1220muA/mum if 9% NFET SOI self-heating effect included) at 200nA/mum off-state current and VDD of 1.0V. PMOS drive current is enhanced by 5% to a value of 575muA/mum (60OmuA/mum if 5% PFET SOI self-heating effect included) which is less than enhancement observed in the NFET due to the differing amount of enhancement of capacitive inversion thickness (TINV) at short channel. With respect to circuit and product performance, this device provides a 5% delay improvement for a product-like ring-oscillator (RO) and results in an improved cross-die statistical distribution of RO delay time. The minimum stable SRAM operating voltage (Vmin) is also significantly improved, indicating that control of the overlap capacitance (Cov) may play a significant role in determining SRAM Vmin. For the first time, we report that the NFET Tinv reduction by LSA is substantially larger at shorter channel lengths which explains the large NFET drive current enhancements obtained by LSA

Novel hybrid metrology for process integration of gate all around (GAA) devices (Conference Presentation)

Multi-channel gate all around (GAA) semiconductor devices require measurements of more target parameters than FinFET devices, due in part to the increased complexity of the different structures needed to fabricate nanosheet devices. In some cases, multiple measurement techniques are required to be used in a hybrid-metrology technique in order to properly extract the necessary information. Optical scatterometry (optical critical dimension, or OCD) is an inline metrology technique which is used to measure the geometrical profile of the structure, but it may not ordinarily be sensitive to very small residues. X-ray based metrologies, such as x-ray fluorescence (XRF) can be used to identify which materials are present in the structure, but are not able to measure profile information for complex 3D structures. This paper reviews a critical etch process step, where neither OCD nor XRF can extract all of the necessary information about the structure on their own, but, when hybridized, are able to provide enough information to solve the application. In GAA structures, the nanosheets are formed from alternating layers of thin SiGe and Si layers which are deposited on a bulk Si substrate. To form the nFET channel, the SiGe must be removed. However, in some cases, there is still remaining SiGe residue on the surface of the Si nanosheets, present in small amounts that are difficult to measure with conventional OCD. Additionally, it is desirable to know at which level of the stacked nanosheets the residue is present. In order to properly characterize the amount of SiGe remaining, data from both OCD and XRF are used. By measuring before and after the etch, the XRF can calculate the percentage of SiGe that is remaining after the etch. This percentage can be used as a constraint in the OCD model to allow the OCD to accurately measure the amount of SiGe, and to enable the OCD model to identify the location of the residue.

A Study of Transient Thermal Spreading of VLSI Packaging With Multi Level Scaling

Trend of VLSI chip power consumption sounds switch over from the Moore’s law to more moderate curve by the “multi core processing” paradigm. Many of the recent advanced VLSI chips adopt the multiple processing units since clock enhancement is no longer feasible to gain the expected performance based on realistic range of power consumption. Even though, heat flux may keep increasing by further fine semiconductor process and may keep localizing by further complex logics. In this study, thermal impact of hot spot size relative to chip size or the dimension of heat sink is investigated by analytic modeling as well as numerical analysis. The analytic transient thermal spreading model in a solid with transfer function has already proposed and was validated in our previous work. In this study, we have considered the impact of thermal interface between the heat source and conductive and spreading component to the sink. Thermal response in wide rage of scales is discussed from transistor level to a millimeter scale. Each level of such various sizes can be investigated individually and can be built up with some sort of cascade manner. Based on this model, thermal diffusion in silicon substrate, which has the thermal coupling with spreader and thermal interface, will be discussed for a further fine process generation of the chip. The result implies that passive thermal spreading can be achieving to the limit.Copyright