Teppo Karema

Design of stable high order 1-bit sigma-delta modulators

A method for designing stable 1-b high-order (>or=3) sigma-delta modulators is presented. The stability analysis is based on the root locus and modeling the quantizer for each clock period at a time. The quantizers gain in the modulator at the present clock period determines the modulators stability for the next clock period. If the modulator is stable during each clock period, it is unconditionally stable and behaves as a linear analog/digital converter. Examples with third-, fourth-, fifth-, and sixth-order sigma-delta modulators are given to explore the use of the proposed method in practice. With the designed sixth-order modulator it is possible to achieve 23-b signal-to-quantization noise ratio at the oversampling ratio of 64.<<ETX>>

An oversampled sigma-delta A/D converter circuit using two-stage fourth order modulator

A sigma-delta analog/digital (A/D) converter realization using a two-stage fourth-order modulator architecture and a fifth-order digital running-sum decimation filter is presented. The analog part of the converter consists of two cascaded second-order modulators. Scaling is used between the sections in order to achieve the modest requirements for component matching and the integrators gain and phase. A digital running-sum filter is used for the decimation to 4f/sub s/ or 2f/sub s/. A dedicated seven-instruction filter processor is designed to perform the final decimation and I/O-communication. The whole system operates on a single 5-V operation voltage.<<ETX>>

Multiplier-free decimator algorithms for superresolution oversampled converters

A class of efficient linear-phase finite impulse response (FIR) decimators for attenuating the out-of-band noise generated by a high-order sigma-delta analog-to-digital modular is introduced. The stopband attenuation of these decimators is more than 120 dB. The decimators contain no general multipliers and a few data memory locations, thereby making them easily VLSI-realizable. This is achieved by using several decimation stages, with each stage containing a small number of delays and arithmetic operations. Some of the stages are constructed using low-order building blocks which are combined to give a selective filter using a few additional tap coefficients and adders. The output sampling rate of these decimators is the minimum possible one, and the proposed decimators can be used, with very slight changes, for many oversampling ratios. These decimators highly attenuate the undesired out-of-band signal components of the input signal, thus significantly relaxing the antialiasing prefilter requirements.<<ETX>>

Fully differential CMOS sigma-delta modulator for high performance analog-to-digital conversion with 5 V operating voltage

The authors present a high-performance second-order sigma-delta modulator for modem and ISDN (integrated-services digital network) analog-to-digital (A/D) conversion applications. The major performance design limiting factors are demonstrated. It is shown that a true 16-bit A/D converter with single 5-V power supply for voice band can be realized with an oversampling ratio of 512; and a 16-bit dynamic range is achieved with an oversampling ratio of 256. The die size of the proposed modulator, using 2.5- mu m CMOS technology, is only 0.56 mm/sup 2/.<<ETX>>

VLSI-realizable multiplier-free interpolators for high-order sigma-delta D/A converters

A class of efficient linear-phase FIR interpolators for superresolution sigma-delta digital-to-analog (D/A) converters are introduced. These interpolators contain no general multipliers and very few data memory locations, thereby making them easily VLSI-realizable. This is achieved by using several interpolation stages with each stage containing a small number of delays and arithmetic operations. The proposed interpolators can be used, with very slight changes, for many interpolation ratios. As an example, an interpolator is designed for a 20-b overall performance in the case of a fifth-order noise shaper.<<ETX>>

A DSP core for speech coding applications

An application specific processor core for mobile speech coding applications has been designed and implemented. Since the architecture is tailored to the application, it has a very low power consumption, making it attractive for handheld devices. The low power consumption, flexible design and high performance have been achieved by a standby mode, optimized full custom design, and a low clock frequency, together with a highly parallel architecture. All the parallelism is accessible to the user on the assembler level. Engineering samples of the processor have been fabricated and tested. The silicon area required for the core is approximately 25 mm/sup 2/ using 1.0 /spl mu/m CMOS. A typical average power consumption for a GSM full rate speech codec implementation using this core is less than 50 mW at 5 V operating voltage, and the complex algorithm is executed in less than 5 ms for each 20 ms speech frame (including encode, decode, VAD and DTX operations).<<ETX>>

A Filter Processor For Interpolation And Decimation

This paper introduces a 92-bit f i l ter processor intended for decimation and interpolation. Considerable improvements in multiplication t ime and silicon area have been achieved by tailoring the hardware for multiplier-free algorithms. T h e prototypes program code realizes a mul t i stage decimator f o r audio 20-bit A / D converter wi th three multi-stage half-band filters and a n equalizer.

A 50 MHz Cascaded Sigma-delta A/d Modulator

A high-performance cascaded sigma-delta modulator circuit with one-bit quantization is introduced. It has a fourth-order topology and provides functionally a 16-bit signal-to-quantization noise with an oaersampling ra- tio of 32. Two modulator circuits have been designed to compare switched-capacitor integrator amplifier structures. One version uses a new dynamically biased class A/B am- plifier topology and the other one is a conventional folded cascade OTA. The prototype was fabricated using a 1.2 mi- cron CMOS technology and it achieves 9 eflective bits with 50 MHz sampling rate.

Oversampled A/D and D/A converters for VLSI system integration

The basic principles of oversampled noise-shaping analog-digital (A/D) and digital-analog (D/A) converters are presented. Basic operation and theory behind sigma-delta modulation are reviewed. The different structures of the sigma-delta converters are described, and the concepts of designing modulators and digital filters are discussed. The latest designs are reviewed.<<ETX>>

An integrated sensor interface circuit for ECG measurements

An integrated circuit for ECG measurements and preprocessing is presented. The circuit consists of four independent macro modules: (1) an analog instrumentation amplifier for ECG tracking, (2) a high-performance sigma-delta A/D converter, (3) a computationally efficient linear-phase digital filter for ECG preprocessing, and (4) an interface for digital and analog ECG output. A bit-serial approach has been chosen for digital modules to keep the circuit area and power consumption sufficiently small. The high-quality modules and versatile output facilities make the circuit very useful in all kinds of ECG monitoring.<<ETX>>